• Title/Summary/Keyword: 장벽금속

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Improved breakdown characteristics of Ga2O3 Schottky barrier diode using floating metal guard ring structure (플로팅 금속 가드링 구조를 이용한 Ga2O3 쇼트키 장벽 다이오드의 항복 특성 개선 연구)

  • Choi, June-Heang;Cha, Ho-Young
    • Journal of IKEEE
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    • v.23 no.1
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    • pp.193-199
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    • 2019
  • In this study, we have proposed a floating metal guard ring structure based on TCAD simulation in order to enhance the breakdown voltage characteristics of gallium oxide ($Ga_2O_3$) vertical high voltage switching Schottky barrier diode. Unlike conventional guard ring structures, the floating metal guard rings do not require an ion implantation process. The locally enhanced high electric field at the anode corner was successfully suppressed by the metal guard rings, resulting in breakdown voltage enhancement. The number of guard rings and their width and spacing were varied for structural optimization during which the current-voltage characteristics and internal electric field and potential distributions were carefully investigated. For an n-type drift layer with a doping concentration of $5{\times}10^{16}cm^{-3}$ and a thickness of $5{\mu}m$, the optimum guard ring structure had 5 guard rings with an individual ring width of $1.5{\mu}m$ and a spacing of $0.2{\mu}m$ between rings. The breakdown voltage was increased from 940 V to 2000 V without degradation of on-resistance by employing the optimum guard ring structure. The proposed floating metal guard ring structure can improve the device performance without requiring an additional fabrication step.

Tunnel Magnetoresistance with Top Layer Plasma Oxidation Time in Doubly Oxidized Barrier Process (이중 절연층 공정에서 상부절연층의 산화시간에 따른 터널자기저항 특성연구)

  • Lee, Ki-Yung;Song, Oh-Sung
    • Journal of the Korean Magnetics Society
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    • v.12 no.3
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    • pp.99-102
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    • 2002
  • We fabricated TMR devices which have doubly oxidized tunnel barrier using plasma oxidation method to form homogeneously oxidized AlO tunnel barrier. We sputtered 10 $\AA$-bottom Al layer and oxidized it with oxidation time of 10 sec. Subsequent sputtering of 13 $\AA$-Al was performed and the metallic layer was oxidized for 50, 80, and 120 sec., respectively. The electrical resistance changed from 500 Ω to 2000 Ω with increase of oxidation time, while variation of MR ratio was little spreading 27∼31 % which is larger than that of TMR device of ordinary single tunnel barrier. We calculated effective barrier height and width by measuring I-V curves, from which we found the barrier height was 1.3∼1.8 eV sufficient for tunnel barrier, and the barrier width (<15.0 $\AA$) was smaller than physical thickness. Our results may be caused by insufficient oxidation of Al precursor into A1$_2$O$_3$. However, doubly oxidized tunnel barriers were superior to conventional single tunnel barrier in uniformity and density. Our results imply that we were able to improve MR ratio and tune resistance by employing doubly oxidized tunnel barrier process.

Computer Analysis of Semiconductor Barrier Characteristics (II) (반도체 접촉장벽 특성의 컴퓨터해석(II)

  • Jong-Woo Park;Keum-Chan Whang;Chang-Yub Park
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.32 no.7
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    • pp.234-238
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    • 1983
  • This paper presents a steady-state computer solution of one-dimensional transport equations, describing a double(metal-semiconductor-metal) contact device, involving only one type of charge carrier. Most of the assumptions and approximations which are ordinarily introduced in order to make the transport equations analytically soluble are avoided here. The results are presented mainly in the form of(a) energy contours (b) concentration contours and (c) I-V characteristics. A computation of differential system capacitance as a function of applied voltage is also presented and schematic corrections are introduced for image force effects.

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Effect of the Surface Roughness of Electrode on the Charge Injection at the Pentacene/Electrode Interface (전극 표면의 거칠기가 펜터신/전극 경계면의 전류-전압 특성에 주는 영향)

  • Kim, Woo-Young;Jeon, D.
    • Journal of the Korean Vacuum Society
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    • v.20 no.2
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    • pp.93-99
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    • 2011
  • We investigated how the surface roughness of electrode affects the charge injection at the pentacene/Au interface. After depositing Au film on the Si substrate by sputtering, we annealed the sample to control the Au surface roughness. Pentacene and Au top electrode were subsequently deposited to complete the sample. The nucleation density of pentacene was slightly higher on the rougher Au electrode, but surface morphologies of thick pentacene films were similar on both the as-prepared and the roughened Au electrodes. The current-voltage curves obtained from the Au/pentacene/Au structure measured as a function of temperature indicated that the interface barrier was higher for the rougher Au bottom-electrode. We propose that the higher barrier was caused by the lower work function of rougher electrode surface and the higher trap density at the interface.

Efficiency Improvement of Al-MIS Solar Cell Using Texturization (Texturization을 이용한 Al-MIS 태양 전지의 효율 개선)

  • Kim, Jin-Seop;Lee, U-Il;Kim, Gi-Wan;Jeong, Ho-Seon
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.19 no.5
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    • pp.26-31
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    • 1982
  • Texturization technique has been employed to improve the efficiency of Al-MIS solar cells. The best condition for the formation of insulating layer was 50$0^{\circ}C$ in N2 ambient for 20 minutes, and the appropriate thickness of the Al barrier metal layer was about 100$\AA$ For the texturization of the face a mixture of hydrazinehydrate and pyrocathecol was used. The efficiency improvement of the texturized cells ranged from 1.2 to 1.6% under 100mW/$\textrm{cm}^2$ illumination.

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Electrical characteristics of GaAs MESFET according to the heat treatment of Ti/Au and Ti/Pd/Au schottky contacts (Ti/Au, Ti/Pd/Au 쇼트키 접촉의 열처리에 따른 GaAs MESFET의 전기적 특성)

  • 남춘우
    • Electrical & Electronic Materials
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    • v.8 no.1
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    • pp.56-63
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    • 1995
  • MESFETs of the Ti/Au and Ti/Pd/Au gate were fabricated on n-type GaAs. Interdiffusion at Schottky interfaces, Schottky contact properties, and MESFET characteristics with heat treatment were investigated. Ti of Ti/Au contact and Pd of Ti/Pd/Au contact acted as a barrier metal against interdiffusion of Au at >$220^{\circ}C$. Pd of Ti/Pd/Au contact acted as a barrier metal even at >$360^{\circ}C$, however, Ti of Ti/Au contact promoted interdiffusion of Au instead of role of barrier metal. As the heat treatment temperature increases, in the case of both contact, saturated drain current and pinch off voltage decreased, open channel resistance increased, and degree of parameter variation in Ti/Au gate was higher than in Ti/Pd/Au gate at >$360^{\circ}C$ Schottky barrier height of Ti/Au and Ti/Pd/Au contacts was 0.69eV and 0.68eV in the as-deposited state, respectively, and Fermi level was pinned in the vicinity of 1/2Eg. As the heat treatment temperature increases, barrier height of Ti/Pd/Au contact increased, however, decreased at >$360^{\circ}C$ in the case of Ti/Au contact. Ideality factor of Ti/Au contact was nearly constant regardless of heat treatment, however, increased at >$360^{\circ}C$ in the case of Ti/Au contact. From the results above, Ti/Pd/Au was stable gate metal than Ti/Au.

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Pt/$\beta$-Sic 접촉의 열처리에 따른 특성변화

  • 나훈주;정재경;엄명윤;김형준
    • Proceedings of the Korean Vacuum Society Conference
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    • 2000.02a
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    • pp.79-79
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    • 2000
  • 탄화규소는 그 전기적, 열적 기계적 안정성 때문에 새로운 반도체 재료로서 주목받고 있는 물질이다. 탄화규소를 이용하여 전자소자를 제조하기 위해서는 ohmic 접촉과 Schottky 접촉을 형성하는 전극물질의 개발이 선행되어야 하며, 고온, 고주파, 고출력용 반도체 소자를 제조하기 위해서는 전극의 고온 안정성 확보가 필수적이다. 따라서 탄화규소 소자의 응용범위는 전극에 의해서 제한된다고 할 수 있다. 일반적으로 전극을 증착한 후 원하는 접촉 특성을 얻기 위해서는 열처리 과정을 거쳐야 하며 접촉의 특성이 열처리에 의해 영향을 받는 것으로 알려져 있다. 따라서 본 연구에서는 열처리가 금속/탄화규소 접촉의 특성에 미치는 영향을 알아보고자 하였으며, 이를 바탕으로 우수한 Schottky 다이오드의 제작 가능성을 타진해보고자 하였다. 유기실리콘 화합물 원료인 TEMSM(bis-trimethysilylmethane)을 사용하여 실리콘 기판위에 단결정 $eta$-Sic 박막을 증착하였다. 기판의 영향을 줄이기 위하여 $\beta$-Sic 박막의 두께가 $1.5mu extrm{m}$ 이상인 시편을 사용하였다. 전극으로는 Pt를 사용하였으며, 전극 증착은 DC magnetron sputter를 이용하였다. 전기적인 특성을 분석하기 위하여 전류-전압, 커패시턴스-전압 특성을 분석하였고, XRD와 AES를 이용하여 계면에서의 반응을 알아보았다. Hall 측정 결과 모든 $\beta$-Sic 박막은 약 2$\times$1018cm-3 정도의 도핑 농도를 갖는 n형 탄화규소임을 확인하였다. Pt/$\beta$-Sic 접촉은 열처리 전에는 ohmic 접촉 특성을 보였으나 열처리 후에는 Schottky 접촉의 특성을 나타냈다. 전기적 특성 분석을 통하여 열처리 온도가 증가할수록 에너지 장벽의 높이가 증가하는 것을 알 수 있었다. 이상적인 Pt/$\beta$-Sic 접촉의 특성을 보이는 것은 전극 증착시 sputtering에 의하여 계면에 발생한 결함이 도너의 역할을 하여 에너지 장벽의 두께를 감소시켜 tunneling을 촉진하기 때문인 것으로 판단된다. 열처리 후 접촉 특성이 변화하는 것은 이러한 결함들의 소멸 때문으로 생각된다. AES 분석을 통하여 열처리시 Pt가 $\beta$-Sic 내부로 확산하는 것을 알 수 있었으며, 이 때 Pt가 $\beta$-Sic 와 반응하여 계면에 실리사이드가 형성됨으로써 Pt/$\beta$-Sic 계면이 보다 안정한 탄화규소 박막 내부로 이동하게 되고 계면의 결함 농도가 줄어드는 것이 접촉 특성 변화의 원인이라 할 수 있다. 열처리 온도가 증가함에 따라 계면이 점점 $\beta$-Sic 내부로 이동하여 결함농도가 낮아지기 때문에 tunneling 효과가 감소하여 에너지 장벽이 높아지게 된다. Pt를 ohmic 접촉과 Schottky 접촉 전극물질로 이용하여 제작한 Schottky 다이오드는 ohmic 접촉 형성시 Schottky 접촉에 발생하는 wputtering 손상에 의하여 좋은 정류특성을 얻지 못하였다. 따라서 chmic 접촉 전에 Schottky 접촉의 passivation이 필요한 것으로 판단된다.

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Change of Schottky barrier height in Er-silicide/p-silicon junction (어븀-실리사이드/p-형 실리콘 접합에서 쇼트키 장벽 높이 변화)

  • Lee, Sol;Jeon, Seung-Ho;Ko, Chang-Hun;Han, Moon-Sup;Jang, Moon-Gyu;Lee, Seong-Jae;Park, Kyoung-Wan
    • Journal of the Korean Vacuum Society
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    • v.16 no.3
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    • pp.197-204
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    • 2007
  • Ultra thin Er-silicide layers formed by Er deposition on the clean p-silicon and in situ post annealing technique were investigated with respect to change of the Schottky barrier height. The formation of Er silicides was confirmed by XPS results. UPS measurements revealed that the workfunction of the silicide decreased and was saturated as the deposited Er thickness increased up to $10{\AA}$. We found that the silicides were mainly composed of Er5Si3 phase through the XRD experiments. After Schottky diodes were fabricated with the Er silicide/p-Si junctions, the Schottky barrier heights were calculated $0.44{\sim}0.78eV$ from the I-V measurements of the Schottky diodes. There was large discrepancy in the Schottky barrier heights deduced from the UPS with the ideal junction condition and the real I-V measurements, so that we attributed the discrepancy to the $Er_5Si_3$ phase in the Er-silicides and the large interfacial density of trap state of it.

Fabrication of 3D Paper-based Analytical Device Using Double-Sided Imprinting Method for Metal Ion Detection (양면 인쇄법을 이용한 중금속 검출용 3D 종이 기반 분석장치 제작)

  • Jinsol, Choi;Heon-Ho, Jeong
    • Clean Technology
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    • v.28 no.4
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    • pp.323-330
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    • 2022
  • Microfluidic paper-based analytical devices (μPADs) have recently been in the spotlight for their applicability in point-of-care diagnostics and environmental material detection. This study presents a double-sided printing method for fabricating 3D-μPADs, providing simple and cost effective metal ion detection. The design of the 3D-μPAD was made into an acryl stamp by laser cutting and then coating it with a thin layer of PDMS using the spin-coating method. This fabricated stamp was used to form the 3D structure of the hydrophobic barrier through a double-sided contact printing method. The fabrication of the 3D hydrophobic barrier within a single sheet was optimized by controlling the spin-coating rate, reagent ratio and contacting time. The optimal conditions were found by analyzing the area change of the PDMS hydrophobic barrier and hydrophilic channel using ink with chromatography paper. Using the fabricated 3D-μPAD under optimized conditions, Ni2+, Cu2+, Hg2+, and pH were detected at different concentrations and displayed with color intensity in grayscale for quantitative analysis using ImageJ. This study demonstrated that a 3D-μPAD biosensor can be applied to detect metal ions without special analysis equipment. This 3D-μPAD provides a highly portable and rapid on-site monitoring platform for detecting multiple heavy metal ions with extremely high repeatability, which is useful for resource-limited areas and developing countries.

A Study on the Dielectric Characteristics and Microstructure of $Si_3N_4$ Metal-Insulator-Metal Capacitors ($Si_3N_4$를 이용한 금속-유전체-금속 구조 커패시터의 유전 특성 및 미세구조 연구)

  • 서동우;이승윤;강진영
    • Journal of the Korean Vacuum Society
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    • v.9 no.2
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    • pp.162-166
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    • 2000
  • High quality $Si_3N_4$ metal-insulator-metal (MIM) capacitors were realized by plasma enhanced chemical vapor deposition (PECVD). Titanium nitride (TiN) adapted as a diffusion barrier reduced the interfacial reaction between $Si_3N_4$ dielectric layer and aluminum metal electrode showing neither hillock nor observable precipitate along the interface. The capacitance and the current-voltage characteristics of the MIM capacitors showed that the minimum thickness of $Si_3N_4$ layer should be limited to 500 $\AA$ under the present process, below which most of the capacitors were electrically shorted resulting in the devastation of on-wafer yield. According to the transmission electron microscopy (TEM) on the cross-sectional microstructure of the capacitors, the dielectric breakdown was caused by slit-like voids formed at the interface between TiN and $Si_3N_4$ layers when the thickness of $Si_3N_4$ layer was less than 500 $\AA$. Based on the calculation of thermally-induced residual stress, the formation of voids was understood from the mechanistic point of view.

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