• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.99-107
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• 2013

Controller area network (CAN) was designed for multiplexing communication between electronic control units (ECUs) in vehicles and thus for decreasing the overall wire harness. The increasing number of ECUs causes the CAN bus overloaded and consequently the error probability of data transmission increases. Since the time duration for the data transmission is proportional to CAN frame length, it is desirable to reduce the frame length. In this paper, a CAN message compression method is proposed using Data Length Code (DLC) and compression area selection algorithm to reduce the CAN frame length and the error probability during the transmission of CAN messages. By the proposed method, it is not needed to predict the maximum value of the difference in successive CAN messages as opposed to other compression methods. Also, by the use of DLC, we can determine whether the received CAN message has been compressed or not without using two ID's as in conventional methods. By simulations using actual CAN data, it is shown that the CAN transmission data is reduced up to 52 % by the proposed method, compared with conventional methods. By using an embedded test board, it is shown that 64bit EMS CAN data compression can be performed within 0.16ms and consequently the proposed algorithm can be used in automobile applications without any problem.

• Journal of the HCI Society of Korea
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• v.9 no.2
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• pp.13-21
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• 2014

Jump-rope is a simple and effective exercise, but its intensive exercise load and monotonous pattern make it difficult to perform consistent workout. On the other hand, jumping rope accompanies large amount of kinetic energy which can be converted into electrical energy. In this study, we designed and implemented a self-powered jump-rope which can support the low-power embedded Bluetooth system inside it. The embedded system wirelessly transmits the acceleration data measured during jumping-rope exercise to a smartphone. We also developed a smartphone app which can count the number of jumps and provide real-time feedback with sound and animated graphic effects in a game context. Pilot test using the prototype smart jump-rope verified that it can be useful to motivation for the jump-rope exercise and make the exercise more effective by providing users with precise information about their exercise. We expect that the developed self-powered jump-rope will change the exercise from an intensive physical activity into electricity-generating fun experience combined with smartphone game, which maximize the benefit of the consistent jump-rope exercise.

• Journal of the Korean Institute of Intelligent Systems
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• v.17 no.2
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• pp.173-178
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• 2007

Recently, fires happen to occur owing to various factors. However, the demage caused by the fire is eyer increasing because timely actions could not be taken. To reduce the demage, a development of fire detection system which makes it possible to take adequate actions is requited. In this work, a sensor network-based fire detection system which utilizes both sensor nodes equipped with smoke sensor and unmaned helicopter is proposed. The proposed system is composed of unmaned helicopter which can gather the measurement data from the deployed sensor nodes and the embedded system which can get visual information on the firing spot and transmit these images to a remote server computer. The proposed system is applied to actual test bed to verify its feasibility.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.185-191
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• 2006

DSRC((Dedicated Short Range Communication) is dedicated short range communication for wireless communications between RSE(Road Side Equipment) and OBE(On-Board Unit) within vehicle moving high speed. In this paper, we implemented 5.8GHz DSRC modem according to Korea TTA(Telecommunication Technology Association) standard and investigated implementation results and design process for SoC(System on a Chip) embedding ARM CPU which control overall signal and process arithmetic work. The SoC is implemented by 0.11um design technology and 480pins EPBGA package. In the implemented SoC ($Jaguar^{TM}$), 5.8GHz DSRC PHY(Physical Layer) modem and MAC are designed and included. For CPU core ARM926EJ-S is embedded, and LCD controller, smart card controller, ethernet MAC, and memory controller are designed as main function.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2004.05a
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• pp.603-606
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• 2004

Automatic test case generation for testing an embedded software is considered. Existing tools for test case generation such as finite state machine or mutant test usually adopt top down approach and depend upon graphical transition and decision table, which makes it difficult to find out where the bugs exist. Also it is hard to describe the special features of embedded systems such as concurrent execution of individual components. Most of embedded systems interacts with the real world, receiving signals through sensors or switches and sending output signals to actuators that somehow manipulate the environment. Embedded software controls the entire system based on the logics such as interpreting the sensor inputs and making the actuators to start or stop their intended operation. This study proposes an automatic test case generation procedure that tests the system starting from the control logics of sensors, switches and actuators and then their concurrent execution controls, and finally the entire system operation. Such a stepwise approach makes it easy to generate test cases to tell where the bugs of embedded software exist.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.3
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• pp.141-152
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• 2007

In this paper, we present a network-oriented lightweight real-time system, which is composed of an event-driven operating system called the Embedded Lightweight Operating System (ELOS) and a generic multi hop ad hoc routing protocol suite. In the ELOS, a conditional preemptive FCFS scheduling method with a guaranteed time slot is designed for efficient real-time processing. For more elaborate configurations, we reinforce fault tolerance by supplementing semi-auto configuration using wireless agent nodes. The developed hardware platform is also introduced, which is a scalable prototype constructed using off-the-shelf components. In addition, in order to evaluate the performance of the proposed system, we developed a ubiquitous network test-bed on which several experiments with respect to various environments are conducted. The results show that the ELOS is considerably favorable for tiny ubiquitous networked systems with real-time constraints.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.64-71
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• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.289-292
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• 2008

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of OpenRISC processor and a clock gating algorithm using ODC (Observability Don't Care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC processor using the proposed algorithm is improved about 8.9% and dynamic power of the processor using samsung $0.18{\mu}m$ technology library is reduced by 13.9%.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.435-444
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• 2006

Recently, various applications of location trigger service have been required and developed as users of location-based services are increasing. The location trigger is detecting event of entering in, existing in or leaving from pre-specified area, and then alerting by short message service, an e-mall or servicing other pre-defined action to mobile subscribers. The conventional methodology of supporting location trigger is detecting location trigger events as periodical requesting location of mobile communication terminal to location gateway server in mobile communication network. But these conventional methods cause mobile communication interruption when the location trigger services are overloaded; thereby inducing performance of core server to be fell off. So in this paper, we have studied a new location trigger technology, named multilevel location trigger, to reduce mobile core network sewer triggering bottleneck and power consumption caused embedded GPS device of mobile phone. Actually, as design and evaluating the performance of location trigger after building test-bed environment, we contribute toward improving echnology of location trigger.