• Title/Summary/Keyword: 임베디드 테스트

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Fault Localization Method by Utilizing Memory Update Information and Memory Partitioning based on Memory Map (메모리 맵 기반 메모리 영역 분할과 메모리 갱신 정보를 활용한 결함 후보 축소 기법)

  • Kim, Kwanhyo;Choi, Ki-Yong;Lee, Jung-Won
    • Journal of KIISE
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    • v.43 no.9
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    • pp.998-1007
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    • 2016
  • In recent years, the cost of automotive ECU (Electronic Control Unit) has accounted for more than 30% of total car production cost. However, the complexity of testing and debugging an automotive ECU is increasing because automobile manufacturers outsource automotive ECU production. Therefore, a large amount of cost and time are spent to localize faults during testing an automotive ECU. In order to solve these problems, we propose a fault localization method in memory for developers who run the integration testing of automotive ECU. In this method, memory is partitioned by utilizing memory map, and fault-suspiciousness for each partition is calculated by utilizing memory update information. Then, the fault-suspicious region for partitions is decided based on calculated fault-suspiciousness. The preliminary result indicated that the proposed method reduced the fault-suspicious region to 15.01(%) of memory size.

Hardware Implementation of Facial Feature Detection Algorithm (얼굴 특징 검출 알고리즘의 하드웨어 설계)

  • Kim, Jung-Ho;Jeong, Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.45 no.1
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    • pp.1-10
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    • 2008
  • In this paper, we designed a facial feature(eyes, a moult and a nose) detection hardware based on the ICT transform which was developed for face detection earlier. Our design used a pipeline architecture for high throughput and it also tried to reduce memory size and memory access rate. The algerian and its hardware implementation were tested on the BioID database, which is a worldwide face detection test bed, and its facial feature detection rate was 100% both in software and hardware, assuming the face boundary was correctly detected. After synthesizing the hardware on Dongbu $0.18{\mu}m$ CMOS library, its die size was $376,821{\mu}m^2$ with the maximum operating clock 78MHz.

Development of Protocol Analyzer Suited for Maintenance of LonWorks Netwo가 for Safety Management of Underground Facilities (지하시설의 안전관리를 위한 LonWorks 네트워크의 유지보수에 적합한 프로토콜 분석기의 개발)

  • Kim, Hyung-Ki;Choi, Gi-Sang;Choi, Gi-Heung
    • Journal of the Korean Society of Safety
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    • v.25 no.6
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    • pp.203-209
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    • 2010
  • A compact ANSI/EIA 709.1 protocol analyzer system suited for maintenance of LonWorks network for safety management of underground facilities was developed and tested. The hardware is based on the TMS320LF2406A embedded system, and the software was designed using Visual C++6.0 under Windows XP environment. Connected to the LonWorks network the developed protocol analyzer decodes the raw packets and pass them to the master PC through USB port. Then on the PC the packets are processed and analyzed in various aspects and the key features that are essential to the maintenance of LonWorks network installed at underground facilities are displayed in a user-friendly format. Performance of the developed protocol analyzer was evaluated through a series of experiments, by measuring the speed of packet analysis and the error rate. The protocol analyzer proved to work reliably even under the increased bandwidth. However, more comprehensive tests under various underground environmental conditions are desired.

OpenGL ES 2.0 Emulation on Desktop PCs (데스크탑 상에서의 OpenGL ES 2.0 에뮬레이션)

  • Baek, Nakhoon
    • KIPS Transactions on Computer and Communication Systems
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    • v.3 no.4
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    • pp.125-128
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    • 2014
  • OpenGL ES(OpenGL for Embedded System) 2.0 is one of the most widely used 3D graphics API(application progrma interface) standard for smart phones and tablet PCs at this time. During programming with this API, they prefer desktop environment rather than the target mobile environment, which has relatively low computing power. Thus, we need to emulate the OpenGL ES 2.0 API on the desktop PCs, where only OpenGL API libraries are available. In this paper, we present technical difficulties and their solutions to emulate OpenGL ES 2.0 on desktop PCs. Our final implementation of OpenGL ES 2.0 emulation library works on desktop PCs and passed over more than 96% of the official CTS(conformance test suites) to prove the correctness of our implementation. Additionally, for the commercially available benchmark programs, our implementation shows equivalent execution speeds to the previous commercial OpenGL ES 2.0 implementations.

The Performance Measurement and Comparison for Real-Time Control Application of ARM920T (ARM920T의 Real-Time 제어적용을 위한 성능 측정 및 비교)

  • Kim, Taek-Ki;Park, Sang-Hyuk;Lim, Jae-Sik;Lee, Young-Il
    • Proceedings of the KIEE Conference
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    • 2008.04a
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    • pp.59-60
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    • 2008
  • In this paper, we investigate the ability of the ARM processor to implement an industrial controller with or without embedded operating system. Discrete-time PID controllers are implemented and tested under various settings e.g. cache on/off, different clock frequencies using S3C2410X chip. A method of real-time application of discrete-time PID controller in WinCE environment is proposed. Based on the test result, we provide the maximum sampling frequencies of PID controller using ARM processor.

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Development of FPGA-based failure detection equipment for SMART TV embedded camera (FPGA를 이용한 SMART TV용 내장형 카메라 불량 검출 장비 개발)

  • Lee, Jun Seo;Kim, Whan Woo;Kim, Ji-Hoon
    • Journal of Korea Society of Industrial Information Systems
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    • v.18 no.5
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    • pp.45-50
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    • 2013
  • Recently, as the market for SMART TV expands, the camera is embedded for providing various user experience. However, this leads to occurrence of camera failure due to TV power up sequence problem, which are usually not detectable in conventional test equipments. Although the failure-detection can be possible by re-generating control signals for audio interface with new equipment, it is expensive and also requires much time to test. In this paper, for SMART TV, FPGA(Field Programmable Gate Array)-based failure-detection system is proposed which can lead to reduction of both cost and time for test.

Implementation of IS-95C Multimedia Terminal using GPS (GPS 연동 IS-95C 멀티미디어 단말기 구현)

  • 하재승
    • Journal of the Korea Computer Industry Society
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    • v.2 no.8
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    • pp.1133-1138
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    • 2001
  • In this paper, we implemented that MMT(Multimedia Terminal) demonstrates spot news, weather forecast, sports news and cultural news employed CDMA mobile communication networks. The MMT displays mobile pictures/joint pictures/on screen ad and to make known Bus stop or Mobile stations. The MMT gives driver's and passenger's safety and valuable information for one's use GPS satellites. We verified to make real time mobile picture transfer use of CDMA2000 1×(IS-95C) network and development the scheduler control each module. This system tested on vehicle that train and bus. MMT was implemented high reliability and stability by the embedded system. The mobile terminal shows reliable data transfer rate about 74Kbps on IS-95C.

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A Speed-up Method of HOG Pedestrian Detector in Advanced SIMD Architecture (Advanced SIMD 아키텍처에서의 HOG 보행자 검출기 고속화 방법)

  • Kwon, Ki-Pyo;Lee, Jae-Heung
    • Journal of IKEEE
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    • v.18 no.1
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    • pp.106-113
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    • 2014
  • A pedestrian detector can be applied for various purposes such as monitoring or counting the number of people in some place, or detecting the people plunging in the driveway. There was a lot of related research. But, the detection speed is slow in embedded system because of the limited computing power. An algorithm for fast pedestrian detector using HOG in ARM SIMD architecture is presented in this paper. There is a way to quickly remove the background of image and to improve the detection speed using NEON parallel technique. When we tested with INRIA Person Dataset, the proposed pedestrian detector improves the speed by 3.01 times than previous one.

Information Technology System-on-Chip (정보기술 시스템온칩)

  • Park, Chun-Myoung
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.05a
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    • pp.769-770
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    • 2011
  • This paper presented a method constructing the ITSoC(Information Technology System-on-Chip). In order to implement the ITSoC, designers are increasing relying on reuse of intellectual property(IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. Also, embedded core in an ITSoC access mechanisms are required to test them at the system level. That is the goal, in theory. In practice, assembling an ITSoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discuss the main challenge in ITSoC designs using IP blocks and elaborates on the methodology and tools being put in place for addressing the problem. It explains ITSoC architecture and gives algorithmic details on the high-level tools being developed for ITSoC design.

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PCB Embedded Triplexer and Dual band/Tri-mode RF Module for US CDMA Handset Applications (북미향 CDMA단말기용 PCB 임베디드된 트리플렉서와 듀얼 밴드/트라이모드 RF 모듈)

  • Lim, Sung-P.;Cheon, Seong-J.;Park, Jae-Y.
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.1384-1385
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    • 2008
  • 본 논문에서는 내장된 수동형 트리플렉서와 듀얼 밴드/트라이모드 RF 모듈을 PCB에 내장시켜서 북미향 CDMA용 부품으로 제작하였다. 수동형 트리플렉서는 모든 수동 소자들을 다층 PCB 기판 안에 내장시키고 그 위에 GPS용 SAW 대역통과필터를 이용하여 설계 및 제작하였다. 8개의 인덕터와 커패시터로 이루어진 수동 회로는 다이플렉서와 병렬 공진기, 임피던스 매칭 회로로 구성되어 있다. CDMA용 듀얼밴드/트라이모드 RF 모듈은 트리플렉서와 CDMA, PCS용 듀플렉서를 테스트 보드 위에 조합하여 제작하였다. 측정된 주파수 특성들은 시뮬레이션 값과 비교적 일치하였다. 트리플렉서와 듀얼 밴드/트라이모드 RF 모듈은 각기 $3{\times}4mm^2$${7\times}7mm^2$의 작은 크기였다. 설계 및 제작된 소자들은 고성능과 경박단소화, 저가화 등의 이점이 있기 때문에, 북미향 CDMA용 단말기의 응용부품에 적용될 수 있을 것으로 예상된다.

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