• The Journal of Korean Association of Computer Education
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• v.21 no.6
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• pp.27-37
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• 2018

In this paper, we propose a design and development method of an elevator simulator that can be used as an embedded application layer software learning tool and a teaching and learning method using it. The simulator provides students with an environment to implement the operating principle and control method of the elevator system in the application layer excluding the issues of hardware and embedded OS layer. This allows students to have a reactive and real-time embedded application development experience. In addition, we present a four-week embedded application software training course with hands-on exercises that add step-by-step functionality using a simulator. As a result of training for actual students, we obtained 83.3 points of learning achievement score and proved that the curriculum has a significant effect on embedded application learning.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.04a
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• pp.665-668
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• 2017

임베디드 소프트웨어의 개발은 실제 어플리케이션이 수행되는 대상 시스템이 아닌 호스트 시스템에서 개발되기 때문에 개발 중 테스팅을 수행하기 어렵다. 또한 대상 시스템에서 어플리케이션이 실행될 때 결함 또는 오류가 발견되면 이를 재현하기 어렵다. 이러한 문제를 해결하기 위한 기존의 연구로는 RTOS 시뮬레이터를 사용하거나 모니터링 시스템을 추가하여 임베디드 소프트웨어의 동작을 확인한다. 하지만 RTOS 시뮬레이터는 기능 테스트만 가능하고 실직적인 시간 추정이 불가능하다. 또한 임베디드 소프트웨어에 모니터링 시스템을 추가하게 되면 어플리케이션의 동작에 영향을 주기 때문에 실시간 시스템의 제약 조건을 확인하기 어렵다. 따라서 본 논문에서는 임베디드 소프트웨어의 RIOS 기반 어플리케이션 구조를 제안하여 호스트 시스템에서 대상 시스템의 테스팅과 모니터링이 가능함을 보인다.

• Journal of the Korea Society of Computer and Information
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• v.18 no.3
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• pp.1-10
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• 2013

In this paper, we propose a method of embedded linux light-weight to improve efficiency of application running on embedded systems. Three methods including fast booting scheme applying the Hibernation technique, JFFS2 file system optimization applying the Symbolic Link and virtual address mapping, kernel light-weight that guarantees the general purpose was applied. Since then check the system dependency and generate kernel image according to the target embedded kit. And embedded system performance of existing linux and linux which the method proposed in this paper was compared. In experimental result, the kernel size was 9.6% improved and the system booting time was 18% improved. And application processing speed on target embedded kit was improved 11% in the best case, 66% in the worst case. This result show that the light-weight method proposed in this paper is guarantee fast booting time and securing resources and it is good for the application processing speed improvement.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.10a
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• pp.141-142
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• 2016

본 논문은 보행자의 이동경로 추적을 위해 PDR(Pedestrian Dead Reckoning) 알고리즘을 탑재한 임베디드 모듈과 연결 가능한 안드로이드 어플리케이션을 구현하였다. 임베디드 모듈은 IMU센서를 통해 얻은 값을 통해 보행자의 위치를 구하고 어플리케이션에 전송한다. 어플리케이션은 임베디드 모듈로부터 위치 값을 받아 스마트폰 화면에 실시간으로 사용자의 위치를 디스플레이 한다. 어플리케이션을 구현하여 필드 테스트를 진행한 결과 보행자의 이동경로를 비교적 정확하게 추적하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1042-1050
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• 2007

This paper describes the system which automatically generates power-minimized embedded cores from MDL descriptions. An automatic generation system is constructed which generated embedded cores which consumes less power for application programs. From the usage information on pipeline stages for each instruction, the proposed system generates embedded cores with the capability of detecting/resolving pipeline hazards. The generated cores are configured such that the power consumption is minimized. The proposed system has been tested by generating HDL codes for ARM9, MIPS R3000 architectures. Experimental results show functional accuracy of the generated cores, and show that power reduction of $20%{\sim}40%$ has been observed for benchmark programs.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10c
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• pp.220-222
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• 2003

최근 무선 임베디드 시스템의 사용이 증가하면서 기존의 분산 환경에 무선 임베디드 시스템이 포함되기 시작하였고, 이를 고려한 분산 어플리케이션들이 개발되고 있다. Global clock과 동기화할 수 있는 GPS가 모든 무선 임베디드 시스템에 장착되지 않은 상황에서 분산된 임베디드 시스템간 혹은 고성능 컴퓨터와의 내부 동기화를 수행할 동기화 기법이 필요하다. 현재 무선환경에서의 동기화에 대한 연구들이 이루어지고 있지만 제한된 리소스의 임베디드 시스템에 그대로 적용하기 어렵다. 이에 본 논문에서는 무선 임베디드 시스템만이 가지는 제한사항을 고려하여 메시지 지연값의 변화량을 측정하여 적용할 수 있는 시간 동기화 기법을 제시하고 실험을 통해 그 성능을 평가한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.337-347
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• 2007

An embedded system is called a multi-mode embedded system if it performs multiple applications by dynamically reconfiguring the system functionality. Further, the embedded system is called a multi-mode multi-task embedded system if it additionally supports multiple tasks to be executed in a mode. In this Paper, we address a HW/SW partitioning problem, that is, HW/SW partitioning of multi-mode multi-task embedded applications with timing constraints of tasks. The objective of the optimization problem is to find a minimal total system cost of allocation/mapping of processing resources to functional modules in tasks together with a schedule that satisfies the timing constraints. The key success of solving the problem is closely related to the degree of the amount of utilization of the potential parallelism among the executions of modules. However, due to an inherently excessively large search space of the parallelism, and to make the task of schedulabilty analysis easy, the prior HW/SW partitioning methods have not been able to fully exploit the potential parallel execution of modules. To overcome the limitation, we propose a set of comprehensive HW/SW partitioning techniques which solve the three subproblems of the partitioning problem simultaneously: (1) allocation of processing resources, (2) mapping the processing resources to the modules in tasks, and (3) determining an execution schedule of modules. Specifically, based on a precise measurement on the parallel execution and schedulability of modules, we develop a stepwise refinement partitioning technique for single-mode multi-task applications. The proposed techniques is then extended to solve the HW/SW partitioning problem of multi-mode multi-task applications. From experiments with a set of real-life applications, it is shown that the proposed techniques are able to reduce the implementation cost by 19.0% and 17.0% for single- and multi-mode multi-task applications over that by the conventional method, respectively.

• Korea Information Processing Society Review
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• v.11 no.6
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• pp.110-116
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• 2004

• The KIPS Transactions:PartA
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• v.14A no.2
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• pp.117-124
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro) TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.