• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1014-1020
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• 2008

Storage devices such as memories are widely used in various electronic products. They require high-density memory and currently the data has been stored in multi-level format, that results in high error rate. In this paper, we apply error correction schemes that are widely used in communication system to the storage devices for satisfying low bit error rate and high code rate. In A WGN channel with average BER $10^{-5}$ and $5{\times}10^{-6}$, we study error correction schemes for 4-1evel cell to achieve target code rate 0.99 and target BER $10^{-11}$ and $10^{-13}$, respectively. Since block codes may perform better than the concatenated codes for high code rate, and it is important to use less degraded inner code even when many bits are punctured. The performance of concatenated codes using general feedforward systematic convolutional codes are worse than the block code only scheme. The simulation results show that RSC codes must be used as inner codes to achieve good performance of punctured convolutional codes for high code rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.4
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• pp.712-720
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• 1994

In digital mobile communication systems, the convolutional coding is considered as the optimum error correcting scheme. Recently, the Viterbi algorithm is widely used for the decoding of convolutional code. Most Viterbi decoder has been proposed in conde rate R=1/2 or 2/3 with memory components (m) less than 3. which degrades the error correcting capability because of small code constraints (K). We consider the design method for typical code rate R=1/2, K=7(171,133) convolutional code with memory components, m=6. In this paper, a novel construction method is presented which combines maximum likelihood decoding with a state transition double detection and comparison method. And the designed circuit has the error-correcting capability of random 2 bit error. As the results of logic simulation, it is shown that the proposed Viterbi decoder exactly corrects 1 bit and 2 bit error signal.

• The KIPS Transactions:PartB
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• v.11B no.2
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• pp.177-186
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• 2004

It is a weak point of the motion estimation technique for video compression that the predicted video encoding algorithm requires higher-order computational complexity. To reduce the computational complexity of encoding algorithms, researchers introduced techniques such as 3D-WT that don't require motion prediction. One of the weakest points of previous 3D-WT studies is that they require too much memory for encoding and too long delay for decoding. In this paper, we propose a technique called `FS (Fast playable and Scalable) 3D-WT' This technique uses a modified Haar wavelet transform algorithm and employs improved encoding algorithm for lower memory and shorter delay requirement. We have executed some tests to compare performance of FS 3D-WT and 3D-V. FS 3D-WT has exhibited the same high compression rate and the same short processing delay as 3D-V has.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.137-146
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• 2006

Shared Memory Multiprocessor (SMP) systems adopting Chip-level MultiThreading (CMT) technology are becoming mainstream servers in commercial applications and High Performance Computining (HPC) applications as well. OpenMP has become the standard paradigm to parallelize applications for SMP mostly because of its ease of use. As the demand for more computing power in HPC applications is growing rapidly, obtaining high performance and scalability for these applications parallelized using OpenMP API's will become more important. In this paper, we study the performance and scalability of HPC applications parallelized using OpenMP, SPEC OMPL (standard OpenMP benchmark suite), on the Sun Fire E25K server which adopts CMT technology. We also study the effect of CMT on SPEC OMPL.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.8-14
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• 2012

Improving the speed of image processing is in great demand according to spread of high quality visual media or massive image applications such as 3D TV or movies, AR(Augmented reality). SIMD computer attached to a host computer can accelerate various image processing and massive data operations. MAMS is a multi-access memory system which is, along with multiple processing elements(PEs), adequate for establishing a high performance pipelined SIMD machine. MAMS supports simultaneous access to pq data elements within a horizontal, a vertical, or a block subarray with a constant interval in an arbitrary position in an $M{\times}N$ array of data elements, where the number of memory modules(MMs), m, is a prime number greater than pq. MAMS-PP4 is the first realization of the MAMS architecture, which consists of four PEs in a single chip and five MMs. This paper presents implementation of image processing algorithms and performance analysis for MAMS-PP16 which consists of 16 PEs with 17 MMs in an extension or the prior work, MAMS-PP4. The newly designed MAMS-PP16 has a 64 bit instruction format and application specific instruction set. The author develops a simulator of the MAMS-PP16 system, which implemented algorithms can be executed on. Performance analysis has done with this simulator executing implemented algorithms of processing images. The result of performance analysis verifies consistent response of MAMS-PP16 through the pyramid operation in image processing algorithms comparing with a Pentium-based serial processor. Executing the pyramid operation in MAMS-PP16 results in consistent response of processing time while randomly response time in a serial processor.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.1
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• pp.97-107
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• 2002

In this paper, we propose the realization of on-line handwritten Chinese character recognition for mobile personal digital assistants (PDA). We focus on the development of an algorithm having a high recognition performance under the restriction that PDA requires small memory storage and less computational complexity in comparison with PC. Therefore, we use index matching method having computational advantage for fast recognition and we suggest a unit reconstruction method to minimize the memory size to store the character models and to accomodate the various changes in stroke order and stroke number of each person in handwriting Chinese characters. We set up standard model consisting of 1800 characters using a set of pre-defined units. Input data are measured by similarity among candidate characters selected on the basis of stroke numbers and region features after preprocessing and feature extracting. We consider 1800 Chinese characters adopted in the middle and high school in Korea. We take character sets of five person, written in printed style, irrespective of stroke ordering and stroke numbers. As experimental results, we obtained an average recognition time of 0.16 second per character and the successful recognition rate of 94.3% with MIPS R4000 CPU in PDA.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.5
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• pp.498-509
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• 2001

Collaborative systems allow users, who may be far removed from each other geographically, to do collaborative work such as 3D animation, computer game, and industrial design in a single virtual space. This paper describes our experience to develop a collaborative system framework that aims at expanding the some functions of a stand-alone visual modeling tool, called 3D Studio Max, into those of the distributed collaborative working environments. The paper mainly deals with design and implementation of a 3D shared-object Plug-In with respect to the 3D Studio Max Plug-In Software Development Kit in the distributed collaborative system developed by the authors. There are two major functions of the proposed scheme; one is to write 3D object-information to the shared memory after extracting it from the 3D Studio Max, the other is to create 3D objects after retrieving them from the shared memory. Also, the proposed scheme provides a simple way of storing 3D objects that have variable size, by means of shared memory which located in between the collaborative system clients and 3D studio Max. One of the remarkable virtures of the Plug-In is to reduce a considerable amount of shared object data which in consequence can mitigate the network overhead. This can be achieved by the fact that the system is able to extract a minimum amount of 3D objects that are required to transmit. Also, using the proposed scheme, user can facilitate 3D Studio Max into distributed collaborative working environments. This, in consequence give many benefits such as saving time as well as eliminating space constraints in the course of 3D modeling when we are under industrial design process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• JOURNAL OF ELECTRICAL WORLD
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• s.323
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• pp.69-75
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• 2003

불투명한 경제정세의 와중에서도 전기에너지를 지탱하는 근간이 되는 파워 일렉트로닉스 분야는 확실히 그 기술개발을 향상시켜 오고 있다. 특히 파워디바이스는, 지구환경과 생활환경을 보다 쾌적하게 하기 위하여 인버터 장치 등의 각종 전력절약기기와 풍력$\cdot$태양광$\cdot$연료전지 등 클린에너지의 전력제어장치에 없어서는 안되는 반도체디바이스로 성장했다. 파워디바이스 중에서도 IGBT(Insulated Gate Bipolar Transistor)의 기술혁신은 요 20년 사이에 비약적인 성과를 거두었다. 1980년대에 제품화된 IGBT는, 반도체메모리의 초미세가공기술을 도입하면서 $5{\mu}m$에서 서브미크론의 디자인툴로 발전하여, 2000년대에 들어 칩의 전류밀도는 약 2배, 포화전압은 약 $65\%$까지 개량되었다. 이와 같은 IGBT의 변천은, 전력손실을 대폭적으로 저감시켜 에너지절약기기의 전력변환효율 향상에 공헌하고 있다. 파워디바이스의 기술진보에서 또 한 가지 잊지 말아야 할 것은 주변회로의 집적화(集積化)에 의한 고성능$\cdot$고기능화이다. 최근의 인버터용 파워디바이스로 가장 많이 사용되고 있는 파워모듈은, IGBT등의 파워칩과 그 주변회로와의 컬래버레이션에 의한 제품이다. 다시 말하면 구동회로, 전류$\cdot$전압$\cdot$온도센서 및 그것들의 보호회로가 IC(집적회로)에 편입되어 고기능$\cdot$소형화를 촉진시키고 있다. 구동회로는 LVIC (저전압집적회로)에서 HVIC(고전압집적회로)로 발전하여 전류$\cdot$온도 등의 각종 센서도 동일 칩에 설계할 수 있게 되었다. 또 센싱이나 보호기능뿐만이 아니라 출력전류의 제어를 위한 연산기능과 di/dt의 제어기능이 내장되도록 되어 있어 보다. 고성능의 인텔리전트 파워모듈(IPM)이라고 불리우는 새로운 개념의 파워디바이스가 실현되었다. 또한 패키지 기술도 내부배선 인덕턴스의 저감과 트랜스퍼 몰드패키지의 개발로, 소형화뿐만이 아니라 파워칩의 성능$\cdot$기능을 충분히 발휘할 수 있도록 개발이 적극적으로 추진되고 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.943-946
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• 2006

XML is the most widely used document format by advantage that self-contained for platform. So, currently the most used among other document format. but XML appeared new problem that memory and transmission. And that be used in environment a request restriction memory and fast transmission as like mobile field. Although discussion of XML binarization is going on progress. And fast Infoset configuration using XML Information Set is receiving attention that a way to lower file size of hold down a existing usage. In this paper, we designed of module using fast Infoset and PER among ASN.1 Encoding Rule for XML binarization. And we implementation of encoder constructed interlace by stage of translation from XML into binary XML.