• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2008.06a
• /
• pp.997-998
• /
• 2008

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.19-24
• /
• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2018.10a
• /
• pp.35-38
• /
• 2018

This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.569-572
• /
• 2014

This paper presents a CMOS switched-capacitor interface circuit for MEMS capacitive sensors. It consist of a capacitance to voltage converter(CVC), a second-order ${\Sigma}{\Delta}$ modulator, and a comparator. A bias circuit is also designed to supply constant bias voltages and currents. This circuit employes the correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques to reduce low-frequency noise and offset. The designed CVC has a sensitivity of 20.53mV/fF and linearity errors less than 0.036%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 5% as the input voltage amplitude increases by 100mV. The designed interface circuit shows linearity errors less than 0.13%, and the current consumption is 0.73mA. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V. The size of the designed chip including PADs is $1117um{\times}983um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.267-270
• /
• 2014

This paper presents a CMOS interface circuit for vibration energy harvesting. The proposed circuit consists of an AC-DC converter and a DC-DC boost converter. The AC-DC converter rectifies the AC signals from vibration devices(PZT), and the DC-DC boost converter generates a boosted and regulated output at a predefined level. A full-wave rectifier using active diodes is used as the AC-DC converter for high efficiency, and a schottky diode type DC-DC boost converter is used for a simple control circuitry. A MPPT(Maximum Power Point Tracking) control is also employed to harvest the maximum power from the PZT. The proposed circuit has been designed in a 0.35um CMOS process. The chip area is $530um{\times}325um$. Simulation results shows that the maximum efficiencies of the AC-DC converter and DC-DC boost converter are 97.7% and 89.2%, respectively. The maximum efficiency of the entire system is 87.2%.

• Journal of Advanced Navigation Technology
• /
• v.21 no.4
• /
• pp.386-393
• /
• 2017

Field programmable gate arrays (FPGAs) are widely used for verification in chip development. In order to verify the circuit programmed to the FPGA, data must be input to the FPGA. There are many ways to communicate with a chip through a PC and an external board, but the simplest and easiest way is to use a universal asynchronous receiver/transmitter (UART). Most recently, most circuits are designed to be internally connected to the advanced microcontroller bus architecture (AMBA) bus. In other words, to verify the designed circuit easily and simply, data must be transmitted through the AMBA bus through the UART. Also the AMBA bus has been available in various versions since version 4.0 recently. Advanced peripheral bus (APB) is suitable for simple testing. In this paper, we design a circuit for UART-to-APB interface. Circuits designed using Verilog-HDL were implemented in Altera Cyclone FPGAs and were capable of operating at speeds up to 380 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.9
• /
• pp.13-21
• /
• 2011

In this paper, the CMOS programmable interface circuit for MEMS gyroscope is presented, and evaluated with the MEMS sensing element. The circuit includes the front-end charge amplifier with 10 bit programmable capacitor arrays, 9 bit DAC for accurate offset calibration, and 10 bit PGA for accurate gain calibration. The self oscillation loop with automatic gain control operates properly. The offset error and gain error after calibration are measured to be 0.36 %FSO and 0.19 %FSO, respectively. The noise equivalent resolution and bias instability are measured to be 0.016 deg/sec and 0.012 deg/sec, respectively. The calibration capability of this circuit can reduce the variations of the output offset and gain, and this can enhance the manufacturability and can improve the yield.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.35T no.1
• /
• pp.48-58
• /
• 1998

For the purpose of designing novel capacitance pressure sensor, several effects on sensitivity such as parasitic capacitance effects, temperature/thermal drift and leakage current have to be eleiminated. This paper proposed the experimental studies on frequency compensation method by electronic circuit technique, C-V converting method with switched capacitor and C-F converting method with schmitt trigger circuit. The third interface circuit by frequency compensation method is composed to eliminate the drift and leakage component by comparision sensing frequency with reference frequency. The signal transmission is realized by digital signal to minimize the influence of noise and high resolution is obtained by means of increasing the number of digital bits. In the fabricated high performance C-V interface, the offset voltage was not appeared, and in case of voltage source, 4.0V, feed back capacitance, 10㎊, the pressure, 0~10 ㎪, the sensitivity of C-V converter is 28 ㎷/㎪.V, the temperature drift characteristic, 0.051 %F.S./$^{\circ}C$ and C-F converter shows -6.6 Hz/pa, 0.078 %F.S./$^{\circ}C$ respectively, relatively good ones.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.9
• /
• pp.47-54
• /
• 2000

We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

• Journal of Sensor Science and Technology
• /
• v.5 no.5
• /
• pp.63-68
• /
• 1996

In order to implement the integrated capacitive pressure sensors, which contains integrated interface circuits to detect the electrical output signal, several main factors that have a bad effect on the characteristics of sensors must be improved, such as parasitic capacitance effects, temperature/thermal drift, and the leakage current of a readout circuitry. This paper describes the novel design of the dedicated CMOS readout circuitry that is consists of two capacitance to frequency converters and 4 bit digital logic compensating circuits. Dividing the oscillation frequency of a sensing sensor by that of reference sensor, this circuit is designed to eliminate the thermal/temperature drift and the effect of the leakage currents, and to access a digital signals to obtain a high signal-to-noise(S/N)ratio. Therefore, the resolution of this circuit can be increased by increasing the number of the digital bits. Digital compensated circuits of this circuits, except for the C-F converters, are fabricated on a FPGA chip, and fundamental performance of the circuits are evaluated.