• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.1-9
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• 2013

This thesis proposes an automatic instruction extension system that utilizes retargetable compiler, based on MDL, to design an ASIP optimized for application. The proposed system uses information gathered from the application program to find all possible expandable instruction candidates. Expandable instruction candidates acquire the realization characteristics through hardware library. The system chooses instruction set and optimizes processor structure satisfying constraints on the bases of hardware characteristics and increase in execution speed. To confirm the efficiency of the proposed system, automatic instruction extension system was performed using various benchmark applications. The proposed system acquired optimized instruction set and processor structure, which are expanded from the commercial version of ARM9TDMI. Experimental results show that number of execution cycle has been reduced by 33.5% when compared to conventional version of ARM9TDMI, while area has been slightly increased.

• Journal of Korean Electronics
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• v.5 no.11
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• pp.60-68
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• 1985

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9A
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• pp.931-939
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• 2007

This paper describes the system which automatically generates instruction-set simulators cores using the SMDL. SMDL describes structure and instruction-set information of a target DSP machine. Analyzing behavioral information of each pipeline stage of all instructions on a target ASIPS, the proposed system automatically generates a cycle-accurate instruction set simulator in C++ for a target processor. The proposed system has been tested by generating instruction-set simulators for ARM9E-S, ADSP-TS20x, and TMS320C2x architectures. Experiments were performed by checking the functions of the $4{\times}4$ matrix multiplication, 16-bit IIR filter, 32-bit multiplication, and the FFT using the generated simulators. Experimental results show the functional accuracy of the generated simulators.

• Journal of Korea Game Society
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• v.13 no.6
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• pp.85-94
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• 2013

Repackaging of mobile games is serious problem in the Android environment. In this paper, we propose a repackaging detection technique using shortened instruction sequence. By using shortened instruction sequence, the proposed technique can be applicable to a mobile device and can block repackaged apps coming from various sources. In the experiment, our technique showed high accuracy of repackaging detection.

• Proceedings of the Korea Society for Simulation Conference
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• 2002.11a
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• pp.73-77
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• 2002

이 논문은 빠른 ASIP(application specific instruction processor) 시뮬레이션을 위한 재적응성을 가진 컴파일드 시뮬레이션 기법에 대해 이야기 한다. 다양한 응용분야에서의 설계 요구사항을 충족시키는 ASIP의 빠른 개발을 위해서, 건전한 설계 방법론 및 고성능의 시뮬레이터가 필요하다. 본 논문에서는 HiX$R^2$라는 ADL(architecture description language)을 이용하여 인스트럭션 수준에서 컴파일드 시뮬레이터를 자동 생성하였다. 컴파일드 시뮬레이션은 시뮬레이션 수행 시 반복되는 인스트럭션 페칭 및 디코딩 부분을 시뮬레이션 런-타임 이전에 미리 수행함으로서 일반적으로 사용되는 인터프리티브 시뮬레이션에 비하여 큰 성능향상을 얻을 수 있다. HiX$R^2$에 기반 한 컴파일드 시뮬레이션은 ARM9 프로세서와 CalmRISC32 프로세서 예제들로 수행하였고, 결과로서 인터프리티브 방식에 비해 150배 이상의 성능향상이 있었다.

• Journal of Korea Society of Industrial Information Systems
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• v.29 no.3
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• pp.79-87
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• 2024

Recently, the importance of pre-trained language models (PLM) has been emphasized for natural language processing (NLP) such as text classification, sentiment analysis, and question answering. Korean PLM shows high performance in NLP in general-purpose domains, but is weak in domains such as finance, medicine, and law. The main goal of this study is to propose a language model learning process and method to build a financial-specific language model that shows good performance not only in the financial domain but also in general-purpose domains. The five steps of the financial-specific language model are (1) financial data collection and preprocessing, (2) selection of model architecture such as PLM or foundation model, (3) domain data learning and instruction tuning, (4) model verification and evaluation, and (5) model deployment and utilization. Through this, a method for constructing pre-learning data that takes advantage of the characteristics of the financial domain and an efficient LLM training method, adaptive learning and instruction tuning techniques, were presented.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.5
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• pp.151-154
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• 2014

An energy of applications had consumed through the complexed inter-action with operating systems, run-time environments, compiler, and applications on various mobile devices. In these days, challenged researches are studying to reduce of energy consumptions that uses energy-oriented high-level and low-level compiler techniques on mobile devices. In this paper, we intented to reduce an energy consumption of Java mobile applications that applied a list instruction scheduling for energy dissipation from dalvik bytecode which extracted Android dex files. Through this works, we can construct the optimized power and energy environment on mobile devices with the limited power supply.

• Proceedings of the Korean Society of Computer Information Conference
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• 2023.01a
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• pp.301-302
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• 2023

에뮬레이션 기술은 다양한 아키텍처에 대해 하드웨어 독립적인 실험 및 분석 환경을 제공하기 때문에 임베디드 기기 분석에 널리 활용되고 있다. 옥테온(Octeon) 아키텍처는 고성능 네트워크 장비에서 주로 사용되는 프로세서로, 이에 대응하는 에뮬레이션 환경의 구축이 어려워 초기 개발 및 분석에 어려움을 겪는다. 따라서 본 논문에서는 QEMU(v.6.0)을 활용한 옥테온 아키텍처의 에뮬레이션 환경을 구현하고 실험한 결과를 소개한다. 구현된 옥테온 에뮬레이션 환경은 옥테온 아키텍처 고유 인스트럭션 중 특정 하드웨어의 지원을 요하지 않는 인스트럭션에 대하여 에뮬레이션이 가능함을 보였으며 이는 옥테온 아키텍처 기반의 기기 프로그램 에뮬레이션에 활용할 수 있을 것으로 기대한다.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.462-470
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• 2011

Retargetability is typically achieved by providing target machine information, ADL, as input. The ADL are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, etc. Simulator are critical components of the exploration and software design toolkit for the system designer. They can be used to perform diverse tasks such as verifying the functionality and/or timing behavior of the system, and generating quantitative measurements(e.g., power energy consumption) which can be used to aid the design process. In this paper, we generate the energy consumption estimation simulator through ADL. For this goal, firstly, we describes the energy consumption estimation and monitoring informations on the ADL based on EXPRESSION. Secondly, we generate the energy estimation and monitoring simulation library and then constructs the simulator, RenergySim. Lastly, we represent the energy estimations results for MIPS R4000 ADL description. From this subjects, we contribute to the efficient architecture developments and prompt SDK generation through programmable experiments in the field of mobile software development.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.