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http://dx.doi.org/10.7840/kics.2013.38B.1.1

Construction of an Automatic Instruction-Set Extension System for Efficient ASIP Design  

Hwang, Deok-Ho (서강대학교 전자공학과 CAD & ES 연구실)
Hwang, Sun-Young (서강대학교 전자공학과 CAD & ES 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.38B, no.1, 2013 , pp. 1-9 More about this Journal
Abstract
This thesis proposes an automatic instruction extension system that utilizes retargetable compiler, based on MDL, to design an ASIP optimized for application. The proposed system uses information gathered from the application program to find all possible expandable instruction candidates. Expandable instruction candidates acquire the realization characteristics through hardware library. The system chooses instruction set and optimizes processor structure satisfying constraints on the bases of hardware characteristics and increase in execution speed. To confirm the efficiency of the proposed system, automatic instruction extension system was performed using various benchmark applications. The proposed system acquired optimized instruction set and processor structure, which are expanded from the commercial version of ARM9TDMI. Experimental results show that number of execution cycle has been reduced by 33.5% when compared to conventional version of ARM9TDMI, while area has been slightly increased.
Keywords
ASIP; MDL; Retargetable compiler; Architecture exploration; Instruction-set extension;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 M. Jain, M. Balakrishnan, and A. Kumar, "ASIP design methodologies : survey and issues," in Proc. IEEE/ACM Int. Conf. VLSI Design. (VLSI 2001), pp. 76-81, Bangalore, India, Jan. 2001.
2 J. B. Cho, Y. H. Yoo, and S. Y. Hwang, "Construction of an automatic generation system of embedded processor cores," J. KICS, vol. 30, no. 6A, pp. 526-534, Jun. 2005.   과학기술학회마을
3 R. Gonzalez, "Xtensa : a configurable and extensible processor," IEEE Micro, vol. 20, no. 2, pp. 60-70, Mar./Apr. 2000.
4 A. Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, and Heinrich Meyr, "A novel methodology for the design of Application-Specific Instruction Set Processors(ASIPs) using a machine description language," IEEE Trans. Computer-Aided Design, vol. 20, no. 11, pp. 1338-1354, Nov. 2001.   DOI   ScienceOn
5 S. Bashford, U. Bieker, B. Harking, R. Leupers, P. Marwedel, A. Neumann, and D. Voggenauer, "The MIMOLA Language Version 4.1," Technical report, University of Dortmund, 1994.
6 A. Fauth, J. Van Praet, and M. Freericks, "Describing instructions set processors using nML," in Proc. European Design & Test Conf., pp. 503-507, Paris, France, Mar. 1995.
7 R. Leupers, M. Hohenauer, J. Ceng, H. Scharwaechter, H. Meyr, G. Ascheid and G. Braun, "Retargetable compilers and architecture exploration for embedded processors," IEEE Proc. Computers and Digital Techniques, vol. 152, no. 2, pp. 209-223, Mar. 2005.   DOI   ScienceOn
8 P. Marwedel and G. Goosens, Code Generation for Embedded Processors, Kluwer Academic Publishers, pp. 14-31, 1995.
9 C. Liem, Retargetable Compilers for Embedded Core Processors, Kluwer Academic Publishers, 1997.
10 R. Leupers, "Compiler design issues for embedded processors," IEEE Design & Test of Computers, vol. 19, no. 4, pp. 51-58, Jul./Aug. 2002.   DOI   ScienceOn
11 A. Alippi, "Determining the optimum extended instruction set architecture for application -specific reconfigurable VLIW CPUs," in Proc. IEEE Int. Workshop on Rapid System Prototyping, pp. 25-27 Jun. 2001.
12 R. Kastner, A. Kaplan, S. Memik, and E. Bozorgzadeh, "Instruction generation for hybrid reconfigurable systems," ACM Trans. Des. Autom. Embed. Syst., vol. 7, no. 4, pp. 605-627, Oct. 2002   DOI   ScienceOn
13 N. Clark, H. Zhong, and S. Mahlke, "Automated custom instruction generation for domain-specific processor acceleration," IEEE Transac. Comput., vol. 54, no. 10, pp. 1258-1270, Oct. 2005   DOI   ScienceOn
14 F. Sun, S. Ravi, A. Raghunathan, and N. Jha, "Custom-instruction synthesis for extensible-processor platforms," IEEE Trans. Comp. Aid. D., vol. 23 no. 2 pp. 216-228. Feb. 2004.   DOI   ScienceOn
15 L. Pozzi, K. Atasu, and P. Ienne, "Exact and approximate algorithms for the extension of embedded processor instruction sets," IEEE Trans. Comp. Aid. D., vol. 25, no. 7, pp. 1209-1229, Jul. 2006.   DOI   ScienceOn
16 P. Yu and T. Mitra, "Scalable custom instructions identification for instruction-set extensible processors," in Proc. Int. Conf. on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 69-78, Sep. 2004,
17 J. Cong, Y. Fan, G. Han, and Z. Zhang, "Application-specific instruction generation for configurable processor architectures," in Proc. ACM/SIGDA Int. Symp. on Field Programmable Gate Arrays, pp. 183-189, Feb. 2004,
18 C. Fraser and D. Hanson, A Retargetable C Compiler : Design and Implementation, Ben-jamin/Cummings, 1995.
19 X. Chen, D. Maskell, and Y. Sun, "Fast identification of custom instructions for extensible processors," IEEE Trans. Comp. Aid. D., vol. 26, no. 2, pp. 359-368. Feb. 2007   DOI   ScienceOn
20 C. Fraser, R. Henry, and T. Proebsting, "BURG - fast optimal instruction selection and tree parsing," ACM SIGPLAN Notices, vol. 27, no. 4, pp. 68-76, Apr. 1992.
21 C. Fraser and D. Hanson, "The lcc 4.x Code-Generation Interface," Microsoft- Research, 2003.
22 J. Ceng, M. Hohenauer, R. Leupers, G. Ascheid, H. Meyr, and G. Braun, "C compiler retargeting based on instruction semantics models," in Proc. Design Automation and Test in Europe, pp. 1150-1155, March. 2005.
23 J. Ceng, W. Sheng, M. Hohenauer, R. Leupers, G. Ascheid, H. Meyr, and G. Braun, "Modeling instruction semantics in ADL processor descriptions for C compiler retargeting". J. VLSI Sig. Proc., vol. 43, no. 2-3, pp. 235-246, Jun, 2006   DOI
24 C. Lee, M. Potkonjak, and W. Mangione-Smith, "MediaBench: a tool for evaluating and synthesizing multimedia and communications systems," in Proc. IEEE/ACM Int. Symp. on Microarchitecture, pp. 330-335, Dec 1997.
25 M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, and T. Mudge, R. Brown, "MiBench: a free, commercially representative embedded benchmark suite," in Proc. IEEE Int. Workshop on Workload Characterization, pp. 3-14, Dec. 2001
26 ARM, ARM922T Technical Reference Manual (rev 0), 2001.