• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1021-1030
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• 2009

We propose optimization method of two-inductor loaded small loop antennas using simple genetic algorithm. To optimize the loop antennas for the RFID and the mobile phone band, we changed positions and values of the two inductors in the loop antenna. Visual basic was used to make genetic algorithm and to calculate fitness values by controlling the commercial EM software. The bandwidth of the optimized RFID loop antenna is 10 MHz at the center frequency of 922 MHz and that of the mobile phone antenna are 84 MHz and 266 MHz at the center frequency of 948 MHz(GSM band) and 1.81 GHz(DCS band), respectively.

• Journal of Navigation and Port Research
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• v.32 no.6
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• pp.481-487
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• 2008

Ship's wireless LAN was in the limelight as equipment of ease, cost reduction, various func tion al i ty. In the paper, a dual-bandpass filter for wireless LAN has proposed, which was designed by using dual-mode square loop resonator with square patch in compliance with 2.4 GHz and 5 GHz band of wireless LAN. The dual-bandpass filter could be designed by adjusting sizes of one perturbation element and three of reference elements in compliance with the frequency bands of 2.4 GHz and 5.8 GHz, Furthermore, new dual-bandpass filter was also designed by adjusting stopband of using open stubs in compliance with the frequency bands of 2.4 GHz and 5.2 GHz. The measured results for the fabricated dual-bandpass filters agreed well with the simulated ones, and hence, it was confirmed that the proposed design method is valid.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.1
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• pp.1-10
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• 2000

본 논문에서는 무정전전원장치(UPS)에 사용되는 3상 PWM 인버터의 정전압 제어특성 향상을 위해 개선된 형태의 데드비트 제어방식을 제안하고 이의 설계를 수행한다. 일반적으로 UPS는 전압제어 루프 안에 전류제어기를 두는 형태의 이중 제어 루프 구조를 가지며, 빠른 과도응답 제어 특성을 얻기 위해 데드비트 제어기가 많이 적용되어 왔다. 그러나 전압, 전류의 이중 제어구조를 갖는 데드비트 제어기의 경우 동일한 극배치 특성으로 인해 기존의 제어 시스템은 불안정한 측면을 갖게된다. 이러한 제어특성의 개선을 위하여 분리된 극배치를 가지는 제어기구조를 제안하며, 이는 전압제어기 출력으로 1차 지수함수 응답을 사용하는 변형된 형태의 데드비트 제어기로 구성된다. 아울러 부하 변동에 따른 부하전류의 외란성분을 전향보상하기 위하여 전차원 외란 관측기를 설계하고 시뮬레이션 및 실험을 통하여 제안된 시스템의 우수성을 확인한다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.437-441
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• 1995

In this paper, the ultra precision positioning system for servo motor and piezo actuator using dual servo loop control has been developed. For positioning system having long distance with ultra precision, the combination of global stage and micro stage is required. Servo moter and ball screw are used as a master stage and piezo acuator as a fine stage. By using this system, an positional precision witin .+-. 30nm has been achieved at dual servo loop control. When using micro stage, an positional precision within .+-. 10nm has been achieved. This result can be applied to develop semiconductor equipment such as wafer stepper.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.54-56
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• 2018

본 논문은 평균 전류 분담 기법을 적용한 UPS(Uninterruptible Power Supply) 시스템의 병렬 운전 기법을 제안한다. 각각의 UPS는 전류 정보를 공유하기 위하여 CAN 통신을 사용하며, 이중 루프 방식의 전압, 전류제어기로 구성되어 있다. UPS의 전류 분담 성능을 내부 전류 제어기의 피드백 전류인 인덕터 전류, 커패시터 전류 그리고 통신 시지연에 따라 영향을 분석하고 3상 30kVA급 UPS에 적용하여 그 유효성을 검증하였다.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.154-163
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• 1999

In this paper, an ultra precision positioning system has been developed using dual servo loop control. For positioning system having long distance with ultra precision , the combination of global stage and micro stage was required. A servo motor based ball screw is used as a global stage and the piezo actuator as a micro stage. For the improvement of positional precision, the digital Chebyshev filter is implemented in the developed to dual servo system. Therefore, the positional repeatability has been achieved within ${\pm}$ 10 mm, and this technique can be applied to develop precision semiconductor equipments such as lithography steppers and probers.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2010.05a
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• pp.674-675
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• 2010

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.408-420
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• 2003

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.

• Journal of IKEEE
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• v.18 no.2
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• pp.220-227
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• 2014

This paper presents a control method of Single-Inductor Dual-Output DC-DC Converter using Common mode feedback and differential feedback loops. To generate duty used for differential mode feedback loop, this paper propose relative sawtooth circuit using current divider circuit which makes ramp signal with variable dead-time. Two outputs of the Single-Inductor Dual-Output DC-DC Converter are specified for 2.8 V and 4.2 V with input voltage 2.5 V. The maximum conversion efficiency of designed SIDO DC-DC Converter is 95% at total output power of 539mW. Cross regulations of Boost1 and Boost2 are 3.57% and 4% each, when increasing twice times output current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.