• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.73-81
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• 2012

In this paper, a novel phase locked loop has been proposed using an analog band-selection loop. When the PLL is out-lock, the PLL has a fasting locking characteristic with the analog band-selection loop. When the PLL is near in-lock, the bandwidth becomes narrow with the fine loop. A frequency voltage converter is introduced to improve a stability and a phase noise performance. The proposed PLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1123-1130
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• 2015

Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.12B
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• pp.2039-2045
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• 2000

본 논문에서는 계산이 간단한 두 가지의 GMSK (Gaussian minimum shift-keying) 변조기들을 제안한다. 제안된 방법들에서는 필터링과 적분과정의 순차적인 처리 대신에, 필터링되는 데이터 계열들에 따른 적분기 출력에서의 위상 성분들을 미리 구하고, ROM (read only memory)에 저장함으로써 계산량을 크게 줄일 수 있다. 첫 번째 방법에서는 필터링되는 심벌들에 따른 각 샘플시점에서의 위상 변화량들이 미리 계산되며, 위상 샘플 값은 필터에 입력되는 데이터 계열에 의한 샘플시점에서의 총 위상 변화량을 구하여 누적함으로써 얻어진다. 두 번째 방법에서는 입력되는 모든 가능한 데이터 계열들에 따른 모든 샘플시점에서의 총 위상 변화량들을 미리 구하여 ROM에 저장하며, 위상 샘플 값은 입력되는 데이터 계열에 따라 샘플시점에 해당하는 총 위상 변화량을 선택하여 누적함으로써 얻어진다. 또한, 두 번째 방법에서는 데이터 계열의 패턴에 따른 총 위상 변화량들의 대칭적인 성질을 이용함으로써 필요한 메모리량을 줄일 수 있다.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.141-146
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• 2016

This paper presents a method to improve time interval error for asynchronous communication systems. The proposed method is designed and simulated with multi-phase VCO, interpolator, phase selector, up-down counter, comparator and adder. The simulation results for CAN communication system show that the maximum time interval error can be tightly managed for satisfying the required specification. The proposed frequency modulation method can be properly used for asynchronous communication systems requiring high reliability.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.246-253
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• 2013

Based on the conventional 2-6GHz digital frequency discriminator (DFD) using the phase unwrapping and least-squares techniques, we propose a new 2-18GHz DFD. To compensate for lowered-precision frequency estimation due to the expanded bandwidth, the proposed DFD design employs more delay lines, accordingly accompanying high complexity. Thus, a new computationally efficient frequency estimation algorithm is also presented to overcome such high computational burden. More specifically, the proposed frequency estimation algorithm is basically based on the conventional phase unwrapping technique, along with a new candidates selection for the unwrapped phases under the condition that the phase margin is known. As a result, the computational burden required for the least-squares technique can be reduced. Finally, simulation results are provided to demonstrate the effectiveness of the proposed approach, compared with those of the conventional DFD's.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.1 s.104
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• pp.17-23
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• 2006

This paper has presented a low phase noise oscillator using a square open loop with microstrip structure. A square open loop resonator has a large coupling coefficient value, which makes a high Q value, and has reduced phase noise. This oscillator has presented the oscillation frequency of 5.84 GHz, harmonics of -15.83 dBc and the phase noise of -111.17 dBc/Hz at the offset frequency of 100 kHz. In conclusion, the proposal structure has improved phase noise of 15 dB at the offset frequency of 100 kHz compared with the conventional structure of oscillator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.5
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• pp.715-722
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• 2000

In this paper, the PLDRO is designed and implemented for X-band. It is comprised of tunable high Q resonator with a varactor diode for frequency tuning, loop filter and a 1/8 prescaler which up to 10GHz. Also, it is implemented a TCXO and a VCO signal into the phase detector and achieved a highly stable signal source. From the measurement, the designed PLDRO has the output power of 2.5dBm at 8GHz and phase noise of -64.33dBc at 10KHz offset from carrier. Its characteristic is 26 dBc. This PLDRO has much better temperature stability.

• Journal of Advanced Navigation Technology
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• v.24 no.5
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• pp.408-414
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• 2020

The method of overcoming the limitation of optical phase conjugator applied into optical long-haul link for transmitting high capacity wavelength division multiplexed (WDM) channels was investigated. The configuration of optical link was based on dispersion-managed link, in which dispersion compensating fiber inserted into each fiber span with single mode fiber, and optical phase conjugator was added into suitable location of link. The maximum number of fiber spans as a function of the launch power of WDM channels in optical link with optical phase conjugator placed at the proposed location was induced and compared for analyzing the compensation performance of the distorted WDM channels. It was confirmed that the more optical phase conjugator depart from the midway of total transmission length, the less the distorted WDM channels was compensated, however, it was also confirmed that the degradation of compensation can be overcome by the suitable value of residual dispersion per span and by the reasonable choice of fiber span controlling total dispersion accumulated in overall transmission link.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.699-702
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• 2012

본 논문에서는 WCDMA(Wide Code Division Multiple Access) 시스템 사양을 만족시키는 주파수 합성기 블록 중 위상잡음 및 전력소모의 최적 설계가 필요한 LC-VCO(voltage controlled oscillator)의 설계를 제안 하였다. 최적 설계를 위한 핵심내용은 LC-tank의 손실성분을 보상하는 MOS트랜지스터의 전달컨덕턴스와 인덕턴스 평면에 여유이득라인과 튜닝 범위 라인을 그어 설계 가능한 영역 내에서 위상잡음이 최소가 되는 인덕턴스 값을 구하고 선택하는 것이다. 제안한 최적 설계방법에 의해 진행된 LC-VCO의 시뮬레이션 결과 위상잡음 특성은 1MHz옵셋에서 -113dBc/Hz였다.