• Korean Journal of Optics and Photonics
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• v.3 no.1
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• pp.27-36
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• 1992

Frequency modulation spectroscopy of the super-cavity, of which finesse is app. 40,000 has been demonstrated by using a sigle mode He-Ne laser. In-phase and quardrature components of frequency modulation signals (FM signal) were obtained by using the 1.5 MHz-driven-electrooptic phase modulator. The vector locus of the FM signa in the phase space, which is consisted of in-phase and quardrature components of the FM signal, was observed and analyzed for the dependence of FM signal upon the phase of the reference signal of a phase-sensitive-detector. According to rotating the phase of the reference signal, the vector locus was observed to rotate with the same phase angle as the reference signal. The in-phase component of the FM signals will be used to stabilize the frequency of the He-Ne laser to the resonant frequency of the super-cavity.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.291-292
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• 2015

본 논문은 계통과 연계된 3상 전압원 인버터를 기반으로 한 BESS의 능동 단독 운전 검출 방법을 제안한다. 계통 전압의 불평형에서도 안정적으로 위상을 추종할 수 있는 DDSRF_PLL(Decoupled Double Synchronous Reference Frame_PLL)방식을 적용 하였으며, 검출된 위상각 정보를 통해 정상분 전류 제어기와 역상분 전류 제어기를 독립적으로 제어할 수 있게 된다. 이를 위해 IEEE 1547과 UL1741에서 제시하는 단독 운전 기준 시험 회로를 구성하여 PSCAD/EMTDC 소프트웨어를 통한 시뮬레이션과 5kw프로토타입 하드웨어 장치를 통해 제안된 단독 운전 검출 방법을 검증하였다.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2006.05a
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• pp.11-16
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• 2006

The object of this study is to develop new examination techniques for detecting the debonds in adhesive interface of different kinds of the material. Ultrasonic signal was modeled by theoretically analyzing ultrasonic propagation phenomenon of the adhesive interface and debonding interface. The test method using the phase reversal of the debonding interface applied to the FRP/Rubber test block. Aluminum/Rubber test block with the flat bottom hole was manufactured to quantitatively evaluate the minimum detection ability of the defects. The pulse echo reflection method and the phase reversal method were mutually compared and it was estimated that the phase reversal method could detect the debonds on the basis of the theoretically predicted ultrasonic signal and ultrasonic test data.

• Journal of the Korean Society of Propulsion Engineers
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• v.13 no.2
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• pp.9-16
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• 2009

The object of this study is to develop new examination technique for detecting debond in adhesive interface of different kinds of materials. Ultrasonic signal was modeled by theoretically analyzing ultrasonic propagation phenomenon of the adhesive interface and debonding interface. The test method using the phase reversal of the debonding interface applied to the FRP/Rubber test block. Aluminum/Rubber test block with the flat bottom hole was manufactured to evaluate quantitatively the minimum detection ability of defects. The pulse echo reflection method and the phase reversal method were mutually compared and it was estimated that the phase reversal method could detect the debond on the basis of the theoretically predicted ultrasonic signal and ultrasonic test data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.6
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• pp.865-870
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• 2001

In this paper, we analyse the effect of phase noise from PLL frequency synthesizer on 64 QAM when detecting corrupted signals. To predict the phase noise of an oscillator very accurately, we assume that the oscillator is linearly time-varying when the input impulsive current to the oscillator is small. The performance of the detector which detects the corrupted signal by oscillator phase noise is compared with that when the detector is only affected by AWGN and then analyse how much the phase noise degrades the system performance for 64 QAM.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.82-86
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• 2009

This work is design of clock and data recovery circuit using system clock. This circuit is composed by PLL(Phase Locked Loop) to make system clock and data recovery circuit. The data recovery circuit using 1/4-rate phase picking Detector helps to reduce clock frequency. It is advantageous for high speed PLL. It can achieve a low jitter operation. The designed CDR(Clock and data recovery) has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and an active area $1{\times}1mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.49-55
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• 2005

In this paper, the phase locked harmonic oscillator(PLHO) using the analog PLL(Phase Locked Loop) is designed and implemented for a wireless LAN system. The harmonic oscillator is consisted of a ring resonator, a varactor diode and a PLL circuit. Because the fundamental fiequency of 8.5 GHz is used as the feedback signal for the PLL and the 2nd harmonic of 17.0 GHz is used as the output, a analog frequency divider for the phase comparison in the PLL system can be omitted. For the simple PLL circuit, the SPD(Sampling Phase Detector) as a phase comparator is used. The output power of the phase locked harmonic oscillator is 2.23 dBm at 17 GHz. The fundamental and 3rd harmonic suppressions are -31.5 dBc and -29.0 dBc, respectively. The measured phase noise characteristics are -87.6 dBc/Hz and -95.4 dBc/Hz at the of offset frequency of 1 kHz and 10 kHz from the carrier, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.191-200
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• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.122-133
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• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

• Journal of Korea Multimedia Society
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• v.3 no.6
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• pp.652-660
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• 2000

This paper proposes a new type of sampling Phase Detector (SPD) for NRZ random bit synchronization circuit. The proposed SPD calculates the mean value of phase difference between bit interval of input signal and period of local reference. Simulated and experimental results show that the proposed SPD is applicable to the phase detector for NRZ random signal. finally the Random NRZ bit synchronization circuit. is designed and implemented by using SPD.