• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.685-691
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• 2003

This paper newly analyzes the effect of the phase noise in the frequency synthesizer on the performance of SFH/M-NCFSK system by standard frequency deviation(equation omitted) when noncoherent FSK demodulation of the square-law detector is considered. We derive the SER in the SFH system and analyze the effect of phase noise on the SFH/M-NCFSK system performance according to the hopping frequency spacing (1/T$\_$h/) and the variation of the standard frequency deviation (equation omitted). The required SNR is about 13.4 dB to meet Ps=10$\^$-3/ when the standard frequency deviation is about 4.0 Hz and the hopping frequency spacing (1/T$\_$h/) in the SFH/2-NCFSK system is 30. So, there is about 2.4 dB power penalty than the phase noise-free system. If the hopping frequency spacing 1/T$\_$h/ is under 30, the error floor may happen and SER considerably grows up. We show that the analytic results closely match with the simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.787-795
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• 1994

In this paper, we have proposed a bit synchronization algorithm which extracts the synchronized clock for random NRZ signal and designed a circuit followed by its performance analysis. The synchronization circuit consists of the Data Transition Detector and Mod 64 Counter, Phase Comparison and Controller, 64 Divider. The data input rate and master clock rate are 16 Kbps and 4.096MHz, respectively. The phase is compensated by 1/64 of the data signal period for every data bit. Through a series of experiments, the maximum immunity of phase jiter for input signal and the deviation of the recovered clock are measured 23.8% and 1.6%, respectively. The fully digital synchronization circuit is simple to implement into signal IC chip and also effective for the low speed digital mobile communications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.61-67
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• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.506-507
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• 2013

본 논문은 단상 전원 시스템에서 입력전원의 위상각 추정에 2차 일반화 적분기(Second-Order Generalized Integrator - SOGI)를 기반으로 하는 적응 필터구조를 적용한다. SOGI 출력은 전원 위상각과 관련되고, 올바른 출력을 위해서는 중심 주파수 ${\omega}^{\prime}$이 전원 주파수를 빠르게 추정할 수 있도록 FLL(Frequency Locked Loop)제어가 필요하다. SOGI-FLL의 기존의 방법과는 다르게 비선형 특성이 강한 주파수 동기화 동특성 모델에 퍼지제어를 적용함으로써 복잡한 선형화 과정이 필요하지 않으며, 실시간 이득 조절로 빠르게 전원 주파수 추정을 할 수 있는데 이는 최종적으로 빠른 전원 위상각 추정을 의미한다. 제안된 방법에 대해서 시뮬레이션을 통하여 그 타당성을 검증한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.7
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• pp.635-645
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• 2016

In this paper, we showed the phase noise of voltage controlled oscillator(VCO) can be radically improved using FLL(Frequency Locked Loop). At first, a 5 GHz VCO is fabricated using a hair-pin resonator. The fabricated VCO shows a phase noise of -53.1 dBc/Hz at 1 kHz frequency offset. In order to improve the phase noise of the fabricated VCO, a FLL is constructed using the feedback loop that consists of the VCO, a frequency detector composed of 5 GHz resonator, loop-filter, and level shifter. The fabricated FLL is designed to oscillate at a frequency of 5 GHz, and its measured phase noise is about -120.6 dBc/Hz at 1 kHz offset frequency. As a result, the phase noise of VCO can be radically improved by about 67.5 dB applying FLL. In addition, the measured phase noise performance is close to that of crystal oscillator.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.3
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• pp.254-260
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• 2000

일반적으로 3상 PWM AC/DC 컨버터는 정상상태에서의 효과적인 오차제거 및 빠른 과도응답 특성을 얻기 위해 동기좌표계상으로 모델링하여 제어한다. 그러나 이와 같은 제어기는 입력전압이 평형일 경우를 전제조건으로 하므로, 입력전압이 불평형일 경우 입력전류와 직류링크 전압에 2차 고조파 성분이 나타나게 된다. 본 논문에서는 불평형 입력전압 하에서 컨버터 시스템의 입력전류와 직류링크 전압에 발생하는 2차 고조파 성분을 최소화하기 위한 새로운 제어기법을 제안하였다. 입력측 역기전력 성분으로 간주할 수 있는 동기좌표계상의 전압을 입력전압의 상태에 따라 변동하였으며, 전류지령치를 무효전력과 2차 고조파 유효전력을 선택적으로 제거하도록 선정하였다. 입력전압의 분석은 동기좌표계상에서 수행되어지며, 각 상의 위상과 진폭의 검출이 불필요하다. 제안한 제어기법은 매우 간단하며 불평형 입력전압 상태에서 입출력 시스템의 고조파 왜란을 효과적으로 제어할 수 있다.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2299-2301
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• 2001

광 디스크의 용량을 증가시기키 위해선, 레이저 다이오드의 단파장화와 렌즈의 개구수 증가가 수년 동안 시도되어왔다. 불행히도 이러한 노력들은 디스크 틸트(tilt)로 인해 야기되는 코마(coma) 수차로 인한 부작용을 유발하였다. 이런 문제를 해결하기 위해, 램(random access memory, RAM) 디스크의 경우 몇 가지 검출과 보상 방법이 제안되었다. 그러나, 롬(read only memory, ROM) 디스크의 경우 아직까지 뚜렷한 해결책이 제시되지 않고 있다. 본 논문에서는 8분할 광 검출기에 의해 생성되는 차동 위상 검출(differential phase detection, DPD) 신호를 이용한 고밀도 롬 디스크에서 래디얼(radial) 틸트를 검출하는 방법을 제안한다. 3축 렌즈 구동형 액츄에이터(actuator)를 이용하여 개발한 래디얼 틸트 서보로 검출된 래디얼 틸트를 보상한다. 액츄에이터의 회전이 트래킹(tracking) 서보(servo)에 미치는 영향을 소개한다. 끝으로 제안된 방법의 유용성을 고밀도 롬 드라이브에 대한 실험을 통해 검증한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.7-13
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• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.2
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• pp.96-104
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• 2009

This paper proposes a single-phase Phase-locked loop (PLL) of the virtual two phase generator using full-order state observer, which is essential to find phase and frequency of the single-phase source. The conventional methods cannot remove the low-order harmonics included in source voltage, which influencesto whole PLL control system. The proposed algorithm separates fundamental wave from harmonics, and removes harmonics effectively. Therefore it generates only the fundamental wave. As it controls virtual voltage and input voltage together, it decreases steady-state error. From simulation and experimental results, the generated frequency by the proposed PLL which it plans, converges to the actual value, and the steady-state error is much reduced under given harmonic voltages. It is also confirmed that the proposed algorithm removed harmonics effectively and it generates only the fundamental wave.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.50-57
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• 2007

A 5Gbps CMOS　adaptive feed-forward equalizer designed for backplane applications is described. The equalizer has adaptive feedback circuits to control the compensating gain of the equalizing filter, which uses a phase detector in clock recovery circuit to detect ISI (Inter-Symbol Interference) level. This makes the equalizer operate adaptively for a various channel length of backplane environments.