• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.191-200
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• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.311-317
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• 2004

A low loss reflection type analog phase shifter which is realized with two varactors and branch coupler. is described. A new design technique for the large phase shift is applied using short stub microstripe lines. This paper presented the realization of design and experimental results. Through the experiment using the duroid microstrip line and varactors, the phase of 2.26GHz signal is controlled to the DC voltage with the phase shift range of 170$^{\circ}$. The achieved insertion loss of less than 3㏈ and the return loss of mote than 12㏈ are achieved over all phase states.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.848-855
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• 2001

본 논문에서는 GHz 대역의 고속 클럭 신호를 필요로 하는 데이터 통신 시스템 분야에 응용될 수 있는 새로운 구조의 클럭 및 데이터 복원회로를 제안하였다. 제안된 회로는 고속의 데이터 전송시 주로 사용되는 NRZ 형태의 데이터 복원에 적합한 구조로서 NRZ 데이터가 주입될 경우에 위상동기 회로에 발생하는 주요 잡음원인인 high frequency jitter를 방지하기 위한 새로운 위상 검출구조를 갖추고 있어서 보다 안정적인 클럭을 제공할 수 있다. 또 가변적인 지연시간을 갖는 delay cell을 이용한 위상검출기를 제안하여 위상 검출기가 갖는 dead zone 문제를 없애고, 항상 최적의 동작을 수행하여 빠른 동기 시간을 갖도록 하였다. Gbps급 대용량의 데이터를 복원하기 위한 클럭 생성을 목표로 하여 CMOS 0.25$\mu\textrm{m}$ 공정을 사용하여 설계한 후 그 동작을 HSPICE post-layout simulation을 통해 검증하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.47-54
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• 1990

In this paper, we design the 4-bit phase shifter which have $22.5^{\circ},45^{\circ},90^{\circ}$ and $180^{\circ}$ phase shift by applying the loaded line and switched network phase shifter. Its phase shift is variable with changing of the stub and passive device parameters. The experiments show the 6.5 dB average insertion loss and $10^{\circ}$ average phase error at center frequency, 6GHz. The results of experiment agree well with the theories except $180^{\circ}$ phase shifter.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.2
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• pp.23-28
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• 1983

In this paper, a method to control the speed of a dc motor using a phase locked loop circuit with a variable sequential filter is discussed. We improved the transient response time more than 15 percent compared to conventional system using a variable sequential filter and the steady state error was reduced to less than 0.05 percent per rotation axis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1973-1981
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• 1994

A PLDRO(Phase Locked Dielectric Resonator Oscillator) in Ku-band(10.95-11.70GHz) is designed with the concept of the feedback property of PLL(Phase Locked Loop). A series feedback type DRO is developed, and VCDRO(Voltage Controlled Dielectric Resonator Oscillator) using a varactor diode as a voltage-variable capacitor is implemented to tune oscillating frequency electrically. Then, PLDRO is designed by using a SPD(Sampling Phase Detector). This PLDRO is phase-locked voltage controlled DRO to reference source(VHF band) by SPD at 10.00 GHz for European FSS(Fixed Satellite Service). The PLDRO generates output power greater than 10dBm at 10.00 GHz and has phase noise of -80 dBc/Hz at 10 KHz offset from carrier. This PLDRO achieves much better frequency stability than conventional VCDRO.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.522-529
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• 2007

A semidynamic frequency divide-by-1.5 MMIC comprises a tunable polyphase filter, tunable image-rejection mixer, and a static divide-by-2 in the feedback path. Wideband suppression of unwanted tones is achieved by employing a tunable image-rejection mixer and a tunable single-stage polyphase filter. Implemented in GaInP/GaAs HBT technology, the divide-by-1.5 MMIC operates over the input frequency range of 4.5 to 9.2 GHz with better than -20 dBc suppressions of $1/3{\times}f_{in}\;and\;f_{in}$ tones, while dissipating 29 mA from 4.1 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.571-575
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• 2017

This paper presents a C-band bi-directional T/R chipset in $0.13{\mu}m$ TSMC CMOS technology for phased array antenna. The T/R chipset, which is a key component of phased array antenna, consists of a 6 bit phase shifter, a 6 bit step attenuator, and three bi-directional gain amplifiers. The phase shifter is controlled up to $354^{\circ}$ with $5.625^{\circ}$ phase step for precise beam steering. The step attenuator is also controlled up to 31.5 dB with 0.5 dB attenuation step for the side lobe level rejection. The LDO(Low Drop Output) regulator for stable 1.2 V DC power and the SPI(Serial Peripheral Interface) for digital control are integrated in the chipset. The chip size is $2.5{\times}1.5mm^2$ including pads.

• Journal of Navigation and Port Research
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• v.27 no.5
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• pp.513-517
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• 2003

In this paper, a VCDRO(Voltage Control Dielectric Resonator Oscillator} applied to X-band as stable source is implementea and constructed with a MESFET for low noise, a dielectric resonator of high frequency selectivity and high Q varactor diode to obtain a good phase noise performance and stable sweep characteristics. The designed circuits is simulated through the harmonic balance simulation technique to provide the optimum performance. The measured results of a fabricated VCDRO show that output is 2.22dBm at 12.05GHz. harmonic suppression -30dBc. phase noise -130dBc at 100kHz offset. and sweep range of varactor diode $\pm$18.7MHz. respectively. This oscillator will be available to X-band application.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.9
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• pp.813-819
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• 2011

In this paper, a new design method of a tunable oscillator using a suspended-stripline resonator is presented. The negative resistance of an FET mounted on microstrip line(MSL) is combined with a high Q suspended-stripline(SSL) resonator to produce a tunable oscillator with good phase noise. The new MSL-SSL transition facilitates the easy connection between the MSL-based circuits and the SSL module. The proposed oscillator is also frequency-tunable using a tuner located on the top of the SSL housing. The measured phase noise of the implemented oscillator at 3.37 GHz is -108.03 dBc@100 kHz and -135.09 dBc@1 MHz with 50 MHz of frequency tuning.