• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.4
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• pp.175-182
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• 2017

In light emitting diode (LED) chip packaging, wire bonding is an important process that connects the LED chip on the lead frame pad with the Au wire and enables electrical operation for the next process. The wire bonding process is divided by two types: thermo compression bonding and ultrasonic bonding. Generally, the wire bonding process consists of three steps: 1st ball bonding that bonds the shape of the ball on the LED chip electrode, looping process that hangs the wire toward another connecting part with a loop shape, and 2nd stitch bonding that forms and bonds to another electrode. This study analyzed the factors affecting the LED die bonding processes to optimize the process capability that bonds a small Zener diode chip on the PLCC (plastic-leaded chip-carrier) LED package frame, and then applied response surface analysis. The design of experiment (DOE) was established considering the five factors, three levels, and four responses by analyzing the factors. As a result, the optimal conditions that meet all the response targets can be derived.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.168-185
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• 2003

This paper presents a progressive algorithm that not only can narrow down the search domain in the course of face identification but also can fast reconstruct various 3D objects from a sketch drawing. The sketch drawing, edge-vertex graph without hidden line removal, which serves as input for reconstruction process, is obtained from an inaccurate freehand sketch of a 3D wireframe object. The algorithm is executed in two stages. In the face identification stage, we generate and classify potential faces into implausible, basis, and minimal faces by using geometrical and topological constraints to reduce search space. The proposed algorithm searches the space of minimal faces only to identify actual faces of an object fast. In the object reconstruction stage, we progressively calculate a 3D structure by optimizing the coordinates of vertices of an object according to the sketch order of faces. The progressive method reconstructs the most plausible 3D object quickly by applying 3D constraints that are derived from the relationship between the object and the sketch drawing in the optimization process. Furthermore, it allows the designer to change viewpoint during sketching. The progressive reconstruction algorithm is discussed, and examples from a working implementation are given.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.6
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• pp.709-713
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• 2005

A new algorithm is proposed for the extraction of line segments to construct 3D wire-frame models of building from the high-resolution aerial images. The purpose of this study Is the accurate and effective extraction of line segments, considering the problems such as discordance of lines and blurred edges existing in the conventional methods. Using the edge map extracted from aerial images, chain code tracking of edges was performed. Then, we extract the line segments considering the strength of edges and the direction of them. SUSAN (Smallest Uni-value Segment Assimilating Nucleus) algorithm proposed by Smith was used to extract an edge map. The proposed algorithm consists of 4 steps: removal of the horizontal, vertical and diagonal components of edges to reduce non-candidate point of line segments based on the chain code tracking of the edge map, removal of contiguous points, removal of the same angle points, and the extraction of the start and end points to be line segments. By comparing the proposed algorithm with Boldt algorithm, better results were obtained regarding the extraction of the representative line segments of buildings, having relatively less extraction of unnecessary line segments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.602-607
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• 2002

In this paper, we proposed an approach to efficiently compress and transmit multiresoltion 3D lariat models for multimedia and very low bit rate applications. A personal facial model is obtained by a 3D laser digitizer, and further re-quantized at several resolutions according to different scope of applications, such as animation, video game, and video conference. By deforming 2D templates to match and re-quantize a 3D digitized facial model, we obtain its compressed model. In the present study, we create hierarchical 2D lariat wireframe templates are adapted according to facial feature points and the proposed piecewise chainlet affined transformation(PACT) method. The 3D digitized model after requantization are reduced significantly without perceptual loss. Moreover the proposed multiresoulation lariat models possessed of hierarchial data structure are apt to be progressively transmitted and displayed across internet.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.9
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• pp.2349-2357
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• 1994

This paper presents a facial expression transformation algorithm and drawing rule generation algolithm for a portrait drawing robot which was developed for the '93 Taejeon EXPO. The developed algorithm was mainly focused on the robust automatic generation of robot programs with the consideration that the drawing robot should work without any limitation of the age, sex or race for the persons. In order to give more demonstratin effects, the facial expression change of the pictured person was performed.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.764-768
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• 1996

와이어 프레임, 면, 솔리드를 하나의 통합된 자료구조에 표현할 수 있는 자료구조를 복합다양체 자료구조라 한다. 기존의 복합다양체 자료구조는 복합다양체에 필요한 방사순환 정보와 디스크 순환정보를 다양체 요소에서도 항상 보유하고 있도록 설계되어 있어 불필요한 정보를 가지고 있었다. 이러한 점을 개선하기 위하여 기본적으로 루프순환 정보를 보유하고 추가로 복합다양체 모서리는 방사순환 정보를, 그리고 복합다양체 꼭지점은 디스크 순환정보를 보유하도록 하는 새로운 자료구조를 제안하였다. 이 새로운 자료구조는 인접 위상 정보 추출에 필요한 3순환 정보를 모두 포함하면서, 자료저장량이 문제시되는 CAD 상세 설계 단계에서 자료량을 줄일 수 있는 장점이 있다.

• Journal of Korean Society of Steel Construction
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• v.22 no.2
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• pp.151-160
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• 2010

The number of cases of collapsed plastic greenhouses in farmlands has increased due to the heavy local snowfall caused by extraordinary atmospheric phenomena. Consequently, the economic losses of farmers have also increased. However the government policy in relation to damage pretension is insufficient and collapse case is repeated every year. The main reason for frame collapse is that the moment capacity of a steel pipe is not sufficient to resist a heavy snowload. In this study, experiments were conducted on the current frame system of a greenhouse with a tension tie. The frame consisted of two sections(${\phi}25.4{\times}1.5$, ${\phi}31.8{\times}1.5$), and its span length was 6.5 m. A temporary tension tie using a steel wire and a fabric rope was connected to the two joints, to which a curved beam and a straight column were connected. The pretension force was applied at the tension tie, and a vertical force simulating snowfall was applied until failure. The fabric rope frame increased the load-carrying capacity by 10-45% compared to the normal frame without a tension tie, and the steel wire frame increased the load-carrying capacity by 58-73% compared to the normal frame without a tension tie. Steel wire was found to be more effective as far as strength is concerned, but its connection details and pretension application are more difficult and complicated than those of the fabric rope. The test results thus show that the fabric rope is more preferable.

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.372-375
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• 2009

반도체 봉지재란 실리콘 칩, 골드와이어, 리드프레임 등의 반도체 소지를 열, 수분, 충격으로부터 보호하기 위해 밀봉하는 재료로서 EMC(Epoxy Moding Compound)가 가장 많이 쓰인다. EMC는 기계적, 전기적 성능향상을 위한 무기재료로 실리카(Silica), 열에 의해 경화되어 3차원 경화구조를 형성하는 에폭시수지, 빠른 경화특성을 부여하기 위한 경화제로서의 페놀수지, 유기재료와 무기재료 사이의 결합력을 높이기 위해 커플링제, 카본블랙, 이형성 확보를 위한 왁스(Wax), 착색제(Colorant), 난연제(Flame Retardant)등의 첨가제로 구성되는 복합소재로써 본 연구에서는 에폭시의 유형에 따른 용융 실리카를 주충진재로 하여 각각의 봉지재의 첨가제를 기준으로 할 때 다양한 형태의 친환경 비할로겐계 반응형 난연제를 합성하는 기술을 개발하고 비 할로겐계 및 Sb 계 첨가형 난연제의 혼용 배합을 통해 친환경 EMC용 난연제의 제조기술을 개발하였다. 이들 EMC의 요구특성은 요구특성은 외부환경으로부터 칩 보호, 칩을 전기적으로 절연특성 유지, 칩의 작동시 발생되는 열의 효과적인 방출 특성 유지, 실장(Board Mounting)의 간편성 특성을 확보해야 하는 특성을 지니고 있어 이들 요구특성에 적합한 특성조사가 함께 이루어졌다.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.1-8
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• 2012

This paper presents a fully-integrated buck converter equipped with packaging inductors. These inductors include parasitic inductances of the bonding wires and lead frames in the package. They have significantly better Q factors than the best on-chip inductors implemented on silicon. This paper also proposes a low-swing gate driver for efficient regulation of high-frequency switching converters. The low-swing driver uses the voltage drop of a diode-connect transistor. The proposed converter is designed and fabricated using a $0.13-{\mu}m$ CMOS process. The fully-integrated buck converter achieves 68.7% and 86.6% efficiency for 3.3 V/2.0 V and 2.8 V/2.3 V conversions, respectively.