• Journal of Korea Multimedia Society
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• v.4 no.5
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• pp.406-413
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• 2001

Ordinary high-speed block matching algorithms have a disadvantage that they need to get MAD (Mean Absolute Distance) as many as the number of search points due to comparing the MAD between the current frame's search block and the reference frame's search block. To solve such disadvantage of high-speed block matching algorithm, the proposed high-speed DS algorithm employs a MMAD calculation method using a specific characteristic that neighboring pixels have almost same values. In this thesis, we can get rid of unnecessary MAD calculation between the search point block by the new calculation method which uses the previously calculated MAD as the current search point and by breaking from the established MAD calculation method which calculates the MAD of a new search point by each search stage. Comparing with the established high-speed block matching algorithm, this new calculation's estimated movement error was shown as similar, and th total calculation amount decreased by $2FN^2Ep$.

• Journal of Korea Multimedia Society
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• v.16 no.12
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• pp.1413-1426
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• 2013

RFID thecnology has been widely adopted by industries for supply chain management. When a product item is manufactured RFID tag is attached to the product item and supply chain management among factories, distributors, retailers and customers needs to handle ownership transfer for the product item carefully. With RFID technology, the secure and efficient ownership transfer protocol is an important issue for the identification of product items and the overall system efficiency on supply chain. Many ownership transfer protocols have been proposed now. They have security problems and use complex operations such as encryption operation and hash function. Lo et al. proposed a protocol using lightweight operations such as shift, addition, XOR, and random number generation[1]. However, this protocol has a security problem in which the secret key between the tag and the new owner is disclosed to the attackers, and it is also weak against the Fraud attack[2]. In this paper, we propose a new ownership transfer protocol using lightweight operations such as shift, addition, and random number generation. This protocol is the modified version of Lo et al.'s protocol and is secure against the security attacks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.594-600
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• 2017

This paper proposes a global search based motion estimation algorithm for high performance HEVC encoder and its hardware architecture. To eliminate temporal redundancy, motion estimation in HEVC inter-view prediction uses global search and fast search algorithm to search for a predicted block having a high correlation with the current PU in an interpolated reference picture. The global search method predicts the motion of all candidate blocks in a given search area, thus ensuring optimal results, but has a disadvantage of large computation time. Therefore we propose a new algorithm that reduces computational complexity by reusing SAD operation in global search to reduce computation time of inter prediction. As a result of applying the proposed algorithm to standard software HM16.12, the computation time was reduced by 61%, BDBitrate by 11.81%, and BDPSNR by about 0.5% compared with the existing search algorithm. As a result of hardware design, the maximum operating frequency is 255 MHz and the total number of gates is 65.1K.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7A
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• pp.547-556
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• 2003

This paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for low-area elliptic curve cryptographic processor. The proposed arithmetic unit, which is linear feed back shift register (LFSR) architecture, is designed by using hardware sharing between the binary GCD algorithm and the most significant bit (MSB)-first multiplication scheme, and it can perform both division and multiplication in GF(2$^{m}$ ). In other word, the proposed architecture produce division results at a rate of one per 2m-1 clock cycles in division mode and multiplication results at a rate of one per m clock cycles in multiplication mode. Analysis shows that the computational delay time of the proposed architecture, for division, is less than previously proposed dividers with reduced transistor counts. In addition, since the proposed arithmetic unit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Therefore, the proposed novel architecture can be used for both division and multiplication circuit of elliptic curve cryptographic processor. Specially, it is well suited to low-area applications such as smart cards and hand held devices.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.4
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• pp.418-423
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• 2004

The motion estimation algorithm based block matching is a widely used in the international standards related to video compression, such as the MPEG series and H.26x series. Full search algorithm(FA) ones of this block matching algorithms is usually impractical because of the large number of computations required for large search region. Fast search algorithms and conventional binary block matching algorithms reduce computational complexity and data processing time but this algorithms have disadvantages that is less performance than full search algorithm. This paper presents new Boolean matching algorithm, called BCBM(Bit Converted Boolean Matching). Proposed algorithm has performance closed to the FA by Boolean only block matching that may be very efficiently implemented in hardware for real time video communication. Simulation results show that the PSNR of the proposed algorithm is about 0.08㏈ loss than FA but is about 0.96∼2.02㏈ gain than fast search algorithm and conventional Boolean matching algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.1
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• pp.10-18
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• 2013

Recently, a fixed complexity LR(fcLR) technique was proposed. Also QR-LRL signal detection method was proposed in which all constellation symbols are tried as the symbol corresponding to the least reliable layer (LRL), thereby achieving high error performance. In this paper, we combine these two efficient methods to propose a novel detection method. When the LRL is disregarded in the process of LR, the worst case complexity of LR is significantly reduced. Also, the proposed method is shown to be superior to the conventional fcLR-based detection method from the perspective of error performance. Simulations are performed to demonstrate the efficacy of the proposed method.

• Journal of IKEEE
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• v.17 no.4
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• pp.418-427
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• 2013

In this paper, we propose a parallel deblocking filter algorithm for H.264/AVC video standard. The deblocking filter has different filter processes according to boundary strength (BS) and each filter process requires various conditional calculations. The order of filtering makes it difficult to parallelize deblocking filter calculations. The proposed deblocking filter algorithm is performed on PRAGRAM which is a 1-D coarse grained reconfigurable architecture (CGRA). Each filter calculation is accelerated using uni-directional pipelined architecture of PRAGRAM. The filter selection and the conditional calculations are efficiently performed using dynamic reconfiguration and conditional reconfiguration. The parallel deblocking filter algorithm uses 225 cycles to process a macroblock and it can process a full HD image at 150 MHz.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1419-1432
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• 1999

The Document Management System(DMS) is a system which retrieves and manages library information efficiently. Since DMS manages the information using only one table, it does not need to provide join and view operations that spend high cost in traditional DBMS. In addition, DMs requires new operations because of their property. the operation has not been supported in existing DBMSs. In this paper we define a data language which represents the structure definition and process of data on the DMS. Especially we define Ranking and Proximity operation which is needed in Document Retrieval,. We also design and implement a query processor to process the query constructed with the data language. When the exiting query processors of relational DBMS are used as a query processor of DMS, they degrade the whole system performance. The proposed query processor not only overcomes such a problem but also supports new operation which is needed in DMS.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.8
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• pp.5579-5585
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• 2015

In FFT(Fast Fourier Transform) implementation, DIT(Decimation-In-Time) and DIF (Decimation-In-Frequency) methods are mostly used. Among them, various DIF structures such as Radix-2/4/8 algorithm have been developed. Compared to the DIF, the DIT structures have not been investigated even though they have a big advantage producing a sequential output. In this paper, a butterfly structure for DIT Radix-8 algorithm is proposed. The proposed structure has smaller latency time because of Radix-8 algorithm in addition to the advantage of the sequential output. In case of 4096-point FFT implementation, the proposed structure has only 4 stages which shows the smaller latency time compared to the 12 stages of Radix-2 algorithm. The proposed butterfly can be used in FFT block required the sequential output and smaller latency time.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.37-50
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• 2007

In this paper, we designed and implementation of the high speed neuron processor for real time object recognition in the making automatic system. and we designed of the PE(Processing Element) used residue number system without carry propagation for the high speed operation. Consisting of MAC(Multiplication and Accumulation) operator using residue number system and sigmoid function operator unit using MAC(Mixed Radix conversion) is designed. The designed circuits are descript by C language and VHDL(Very High Speed Integrated Circuit Hardware Description Language) and synthesized by compass tools and finally, the designed processor is fabricated in $0.8{\mu}m$ CMOS process. we designed of MAC operation unit and sigmoid proceeding unit are proved that it could run time 0.6nsec on the simulation and improved to the speed of the three times and decreased to hardware size about 50%, each order. The designed neuron processor can be implemented of the object recognition in making automatic system with desired real time processing.