• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.72-79
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• 2003

This paper proposes a 32${\times}$32 Modified Booth multiplier using CMOS multiple-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 67.1% and 37.3%, compared with that of the voltage mode binary multiplier and the previous multiple-valued logic multiplier, respectively. The multiplier is designed with a 0.35${\mu}{\textrm}{m}$ standard CMOS technology at a 3.3V supply voltage and unit current 10$mutextrm{A}$, and verified by HSPICE. The multiplier has 5.9㎱ of propagation delay time and 16.9mW of power dissipation. The performance is comparable to that of the fastest binary multiplier reported.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.3
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• pp.270-279
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• 2000

This paper describes the on-chip learning algorithm of neural networks using the stochastic pulse arithmetic. Stochastic pulse arithmetic is the computation using the numbers represented by the probability of 1' and 0's occurrences in a random pulse stream. This stochastic arithmetic has the merits when applied to neural network ; reduction of the area of the implemented hardware and getting a global solution escaping from local minima by virtue of the stochastic characteristics. And in this study, the on-chip learning algorithm is derived from the backpropagation algorithm for effective hardware implementation. We simulate the nonlinear separation problem of the some character patterns to verify the proposed learning algorithm. We also had good results after applying this algorithm to recognize printed and handwritten numbers.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.1
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• pp.95-103
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• 2009

We improve the performance of WCDMA repeater by cancelling the feedback interference radio signal under the fixed point implementation. Floating-point DSP or FPGA to implement the ICS algorithm may have an disadvantage of high cost, To solve this problem, we suggest the ICS algorithm based on LMS under fixed point operation, and show the validity of our results by comparing with the floating-point results through numerical simulation.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1992.04b
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• pp.415-424
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• 1992

본 논문에서는 정수선형계획법을 반도체 설계자동화과정에 이용한 예를 보인다. 반도체 설계자동화과정은 매우 여러 단계를 거치게 되는데, 본 논문에서는 상위수준 합성중 스케쥴링(scheduling)문제에 정수선형계획법을 응용하였다. 여기서 스케쥴링 문제는 설계자동화의 초기단계에서 알고리듬으로 주어진 입력을 하드웨어 요소들로 표현하는 과정에서 매 제어단계(control step)에서 수행하여야 할 연산내용을 결정하는 문제이다. 스케쥴링의 목적함수는 주어진 제어단계 갯수내에서 하드웨어 비용의 최소화이다. 이를 위해 우선 ASAP(As Soon As Possible)과 ALAP(As Late As Possible)방법을 이용하여 매 연산의 수행시작이 가능한 가장 빠른 시간과 가장 늦은 시간을 구한다. 이 두 시간 사이가 각 연산의 time frame이 되며 이를 이용하여 스케쥴링 문제를 정수 선형 계획법으로 공식화하여 풀었다. 이 공식화는 chaining, multicycle연산, pipeline data path, pipeline기능 유닛등에도 일반화하여 적용가능함을 보인다. 실험을 통해 본 공식화 방법이 기존 알고리듬에 의한 해보다 우수한 해를 제공함을 보인다. 비교를 위해 잘 알려진 benchmark회로인 bandpass filter를 이용하였는데 이 회로는 8개의 덧셈, 7개의 뺄셈 및 12개의 곱셈연산을 포함하고 있다. 제시된 알고리듬은 이 회로를 8개의 제어단계내에 총비용 675 (연산별 하드웨어 비용은 라이브러리로 주어짐)로 스케쥴링하였는데 이는 기존의 최상의 결과인 685보다 우수한 결과이다.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.1_2
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• pp.1-10
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• 2001

본 논문에서는 부쉬 트리를 할당 트리로 변환한 후 결합 연산을 수행하면서 실제 실행시간을 동적으로 계산하고 그 결과에 의해 실시간에 프로세서를 할당하는 동적 프로세서 할당 기법을 이용한 파이프라인 해쉬 결합 알고리즘을 제안하였다. 프로세서를 할당하는 과정에서 초기 릴레이션의 기본 정보만을 이용하여 미리 프로세서를 할당하는 기존의 정적 프로세서 할당 기법은 정확한 실행시간을 예측할 수 없었다. 따라서 본 논문에서는 할당 트리 각 노드의 실행결과를 포함한 결합 과정 중의 정보를 다음 노드의 실행시간에 충분히 반영하는 동적 프로세서 할당 기법을 제안하였으며, 이로써 프로세서를 효율적으로 분배하고 전체적인 실행시간을 최소화하였다. 또한 전체적인 질의 실행시간을 줄이기 위하여 결합 가능성이 없는 튜플들을 제거한 후 결합 연산을 수행할 수 있도록 해쉬 필터 기법을 이용하였다. 결합 연산을 수행하기에 앞서 모든 결합 속성 값에 대해 해쉬 필터를 생성하는 정적 필터 기법은 모든 결합 연산의 중간 결과로 발생할 수 있으나 최종 결과 릴레이션의 튜플이 될 수 없는 튜플들까지도 모두 추출이 가능하다. 따라서 각각의 결합 연산 직전에 해쉬 필터를 생성하는 동적 필터 기법에 비해 결합 가능성이 없는 튜플을 최대한 제거할 수 있으며 이로써 결합 연산의 실행비용을 크게 줄일 수 있었다.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.12-18
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• 2017

This paper presents a Dijkstra's-search-based sphere decoding (SD) algorithm with limited complexity for the symbol detection in MIMO communication systems. The Dijkstra search-based SD is efficient to achieve a near-optimal error rate in the MIMO symbol detection, but has a critical problem in that its complexity is variable and can correspond to that of the exhaustive search in the worst case. The proposed algorithm limits the computations while achieving a near-optimal error rate. Simulation results show that the error rate is near optimal even with the limited complexity.

• Journal of the Korea Computer Industry Society
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• v.3 no.2
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• pp.149-158
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• 2002

This paper deals with design and verification of an arithmetic logic unit(ALU) to be used for development of optical computers. The ALU is based on optical switching device, $LiNbO_3$, which is easy to interface with electronic technology and most common in the market. It consists of an arithmetic/logic circuit performing logic operations, memory devices storing operands and the results of operations, and supplementary circuits to select instruction codes, and operates in bit-serial manner. In addition, a simulator is developed for verification of the design, and a set of basic instructions are executed in sequence and step-by-step changes in the accumulator and the memory are examined through simulations, to show that various operations are performed correctly.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.669-679
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• 2013

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.62-71
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• 2002

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture for high-speed FFT. the instructions perform new operation flows, which are different from the MAC (Multiply and Accumulate) operation on which existing DSP chips heavily depend. The proposed DPU (Data Processing Unit) supporting the instructions shows two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 ${\mu}m$ standard cell library. The maximum operating clock frequency is about 144.5 MHz.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.5
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• pp.17-23
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• 2004

In this paper, we proposed a mixed algerian to improve decimal division speed. In the binary number system, nonrestoring algorithm has a smaller number of operation than restoring algorithm. In decimal number system however, the number of operations differs with respect to quotient values. Since one digit ranges 0 to 9 in decimal, the proposed mixed algerian employs both nonrestoring and restoring algorithm considering current partial remainder values. The proposed algorithm chooses either restoring or nonrestoring algerian based on the remainder values. The proposed algorithm improves computation speed substantially over a single algorithm decreasing the number of operations.