• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.68-77
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• 2003

An improved negative capacitance circuit that cancels out input impedance of a front-end in a bioimpedance measurement and operates stably with a low gain margin has been proposed. Since the proposed circuit comprises wide-band operational amplifiers, selecting operational amplifiers is easy, while an operational amplifier of prefer bandwidth should be chosen to apply conventional circuit. Also, since gain margin can be controlled by a feedback resistor connected serially with a feedback capacitor, gain margin is tuneable with a potentiometer. The input impedance of the proposed circuit is two times larger than that of the conventional circuit and 40-times than that without a negative capacitance circuit. Furthermore, closed-loop phase response of the proposed circuit is better than that of the conventional circuit or without a negative capacitance circuit. Above all, for the proposed circuit, the frequency at which a gain peaking occurs is higher than the frequency at which the loop gain becomes a maximum. Thus, the proposed circuit is not affected by a gain peaking and can be operated with a very low gain margin.

• Journal of the Korea Society of Computer and Information
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• v.17 no.3
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• pp.1-10
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• 2012

A low-complexity Multiplication over GF(2m) and multiplier circuit has been proposed by using cyclic-shift coefficients and the irreducible trinomial. The proposed circuit has the parallel input/output architecture and shows the lower-complexity than others with the characteristics of the cyclic-shift coefficients and the irreducible trinomial modular computation. The proposed multiplier is composed of $2m^2$ 2-input AND gates and m (m+2) 2-input XOR gates without the memories and switches. And the minimum propagation delay is $T_A+(2+{\lceil}log_2m{\rceil})T_X$. The Proposed circuit architecture is well suited to VLSI implementation because it is simple, regular and modular.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.2
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• pp.81-86
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• 2006

In this paper, a new process detection circuit is proposed. The proposed process detection circuit compares a long channel MOS transistor (L > 0.4um) to a short channel MOS transistor which uses lowest feature size of the process. The circuit generates the differential current proportional to the deviation of carrier mobilities according to the process variation. This method keep the two transistor's drain voltage same by implementing the feedback using a high gain OPAMP. This paper also shows the new design of the simple high gam self-biased rail-to-rail OPAMP using a proposed self-biased super MOS composite circuit. The gain of designed OPAMP is measured over 100dB with $0.2{\sim}1.6V$ wide range CMR in single stage. Finally, the proposed process detection circuit is applied to a differential VCO and the VCO showed that the proposed process detection circuit compensates the process corners successfully and ensures the wide rage operation.

• Proceedings of the Optical Society of Korea Conference
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• 2005.02a
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• pp.304-305
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• 2005

두께가 있는 물체의 단면영상을 얻는 기술은 현대 영상 기술에서 가장 도전적인 관제 중 하나이다. 특히 광학현미경을 이용해 물체의 단면 영상을 얻기 위해 특정 단면에 초점을 맺을 경우 초점 맺어지지 않은 면으로부터 산란되어오는 빛은 탈 초점잡음(defocused noise)으로 작용한다. 이번 발표에서는 물체의 복소 홀로그램 정보를 광 스케닝 홀로그램 방법을 이용하여 추출하고 그를 수치적인 방법으로 연산해 탈 초점 잡음을 제거한다.

• Proceedings of the Optical Society of Korea Conference
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• 2009.10a
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• pp.117-118
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• 2009

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.4
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• pp.19-24
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• 1974

An ungrounded inductance, necessary for construction of general type networks, is synthesized using two operational amplifiers and several passive elements. Through indefinite admittance matrix procedure. it is proved that the synthesized network is equivalent to an ungrounded pure inductance with a positive and a negative resistance in the parallel arms. A practical low-pass filter is made according to this synthesis method, and the resultant characteristic has been verified by means of IBM's simulation program ECAP (Electronic Circuit Analysis Program).

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.245-248
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• 2001

본 논문에서는 연집 오류(burst error)에 우수한 정정 능력을 보이는 고속 RS(Reed-Solomon) 복호기를 제안한다. 제안된 RS 복호기는 RS(n, k, t); (37 < n ≤ 255, 21 < k ≤ 239, t = 8)의 사양을 지원하며 수정 유클리드 알고리즘(modified Euclid´s algorithm)을 이용한 시스톨릭 어레이(systolic array) 방식의 병렬처리 구조로 설계되었다. 고속 RS 복호기의 효율적인 VSLI 설계를 위하여 새로운 방식의 수정 유클리드 알고리즘 연간 회로를 제안한다. 제안된 수정 유클리드 알고리즘 회로는 2t + 1의 연산 지연 시간을 갖으며 기존 구조의 연산 지연 시간인 3t + 37에 비하여 t = 8 인 경우 약 72%의 연산 지연이 감소하였다. 제안된 구조를 VHDL을 이용하여 설계하였으며 SAMSUNG 0.5㎛(KG80) 라이브러리를 이용하여 논리 합성과 타이밍 검증을 수행하였다. 합성된 RS 복호기의 총 게이트 수는 약 77,000 개이며 최대 80MHz의 동작 속도를 나타내었다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09b
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• pp.122-125
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• 2003

By advent of NNC(Neural Network Chip), it is possible that process in parallel and discern the importance of signal with learning oneself by experience in external signal. So, the design of general purpose operation unit using VHDL(VHSIC Hardware Description Language) on the existing FPGA(Field Programmable Gate Array) can replaced EN(Expert Network) and learning algorithm. Also, neural network operation unit is possible various operation using learning of NN(Neural Network). This paper present general purpose operation unit using hierarchical structure of EN EN of presented structure learn from logical gate which constitute a operation unit, it relocated several layer The overall structure is hierarchical using a module, it has generality more than FPGA operation unit.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.89-93
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• 2002

This paper describes an ALU core which is suitable for 32-bit DSP This ALU operates in 32-bit data and occupies the third stage, execution, among 5 stage pipeline structure. The supplied functions of the ALU are arithmetic operations, logical operations, shifting, and so on. For the implementation of this ALU core, each functional block is described by HDL. And the functional verification of the ALU core is performed through HDL simulation. This ALU is designed to use the 32-bit DSP.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.6
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• pp.38-43
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• 1981

In this paper an actively compensatedfinite gain amplifie. (FGA) with positive gain using 4 operational amplifiers and resistors is propo sod, and an application is considered in an active RC filter. By cancelling the effect of the GB's up to the third-order term of s on the transfer function, the proposed FGA has the extended frequency range over that of the FGA using 3 operational amplifiers. When this FGA is applied to an active RC filter with Pole frequncy of 100kHz, the magnitude error of the frequency characteristics of the filter is less than 2%.