• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.11-20
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• 2007

A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].

• Journal of KIISE:Databases
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• v.31 no.5
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• pp.479-491
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• 2004

Location information of mobile objects is applied to vehicle tracking, digital battlefields, location based services, and telematics. Their location coordinates are periodically measured and stored in the application systems. The linear function is mainly used to estimate the location information that is not in the system at the query time point. However, a new method is needed to improve uncertainties of the location representation, because the location estimation by linear function induces the estimation error. This paper proposes an application method of the cubic spline interpolation in order to reduce deviation of the location estimation by linear function. First, we define location information of the mobile object moving on the two-dimensional space. Next, we apply the cubic spline interpolation to location estimation of the proposed data model and describe algorithm of the estimation operation. Finally, the precision of this estimation operation model is experimented. The experimentation comes out more accurate results than the method by linear function, although the proposed location estimation function uses the small amount of information. The proposed method has an advantage that drops the cost of data storage space and communication for the management of location information of the mobile objects.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.3
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• pp.70-79
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• 2007

H.264/AVC has many repeated computation for motion estimation. Because of that, it takes much time to encode and it is very hard to implement into a real-time encoder. Many fast algorithms were proposed to reduce computation time but encoding quality couldn't be qualified. In this paper we proposed a new motion vector prediction method for efficient and fast full search H.264/AVC motion estimation. We proposed independent motion vector prediction and SAD share for motion estimation. Using our algorithm, motion estimation reduce calculation complexity 80% and less distortion of image (less PSNR drop) than previous full search scheme. We simulated our proposed method. Maximum Y PSNR drop is about 0.04 dB and average bit increasing is about 0.6%.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.4
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• pp.121-130
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• 2004

In the application requiring the interoperability of different networks such as VoIP and wireless communication system, two speech codecs must work together with the structure of cascaded connection, tandem. Tandem has several problems such as long delay, high complexity and quality degradation due to twice complete encoding/decoding process. Transcoding is one of the best solutions to solve these problems. Transcoding algorithm is varied with the structure of source and target coder. In this paper, transcoding algorithm including the LSP conversion, the pitch estimation and new perceptual weighting filter for reducing complexity and improving qualify is proposed. These algorithms are applied to the pair of AMR md G.723.1. By employing the proposed algorithms in the transcoder, the complexity is reduced by about 20%-58% and quality is improved compared to tandem.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.23-30
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• 2008

Recently, a considerable number of studies have been conducted on pairing based cryptosystems. The efficiency of pairing based cryptosystems depends on finite fields, similar to existing public key cryptosystems. In general, pairing based ctyptosystems are defined over finite fields of chracteristic three, GF($3^m$), based on trinomials. A multiplication in GF($3^m$) is the most dominant operation. This paper proposes a new most significant digit(MSD)-first digit- serial multiplier. The proposed MSD-first digit-serial multiplier has the same area complexity compared to previous multipliers, since the modular reduction step is performed in parallel. And the critical path delay is reduced from 1MUL+(log ${\lceil}n{\rceil}$+1)ADD to 1MUL+(log ${\lceil}n+1{\rceil}$)ADD. Therefore, when the digit size is not $2^k$, the time delay is reduced by one addition.

• The KIPS Transactions:PartD
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• v.17D no.6
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• pp.395-404
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• 2010

Solid-State Disks (SSDs) have been currently considered as a promising candidate to replace hard disks, due to their significantly short access time, low power consumption, and shock resistance. SSDs, however, have drawbacks such that their write throughput and life span are decreased by random-writes, nearly regardless of SSDs controller designs. Previous studies have mostly focused on better designs of SSDs controller and reducing the number of write operations to SSDs. We suggest another method that reallocates data pages that tend to be simultaneously written to contiguous blocks. Our method gathers write operations during a period of time and generates write traces. After transforming each trace to a set of transactions, our method mines frequent itemsets from the transactions and reallocates the pages of the frequent itemsets. In addition, we introduce an algorithm that reallocates the pages of the frequent itemsets with moderate time complexity. Experiments using TPC-C workload demonstrated that our method successfully reduce 6% of total logical block access.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.969-972
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• 2016

In this paper, we propose an algorithm of angular mode selection for high-performance HEVC intra prediction. HEVC intra prediction is used to remove the spatial redundancy. Intra prediction has a total of 35 modes and block size of $64{\times}64$ to $4{\times}4$. Intra prediction has a high amount of calculation and operational time due to performing all 35 modes for each block size for the best cost. The angular mode algorithm proposed has a simple difference between pixels of the original image and the selected angular mode. A decision is made to select one angular mode plus planar mode and DC mode to perform the intra prediction and determine the mode with the best cost. In effect, only three modes are executed compared to the traditional 35 modes. Performance evaluation index used are BD-PSNR and BD-Bitrate. For the proposed algorithm, BD-PSNR results averagely increased by 0.035 and BD-Bitrate decreased by 0.623 relative to the HM-16.9 intra prediction. In addition, the encoding time is decreased by about 6.905%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10C
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• pp.1000-1010
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• 2006

This paper proposes a new architecture for DCT-based motion estimation and compensation. Previous methods do riot take sufficient advantage of the sparseness of 2-D DCT coefficients to reduce execution time. We first derive a recursion equation to perform DCT domain motion estimation more efficiently; we then use it to develop a wavefront array processor (WAP) consisting of processing elements. In addition, we show that the recursion equation enables motion predicted images with different frequency bands, for example, from the images with low frequency components to the images with low and high frequency components. The wavefront way Processor can reconfigure to different motion estimation algorithms, such as logarithmic search and three step search, without architectural modifications. These properties can be effectively used to reduce the energy required for video encoding and decoding. The proposed WAP architecture achieves a significant reduction in computational complexity and processing time. It is also shown that the motion estimation algorithm in the transform domain using SAD (Sum of Absolute Differences) matching criterion maximizes PSNR and the compression ratio for the practical video coding applications when compared to tile motion estimation algorithm in the spatial domain using either SAD or SSD.

• Journal of the Korea Society of Computer and Information
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• v.26 no.6
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• pp.1-8
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• 2021

In this paper, we propose reinforced VGG style network structure for low performance embedded system to classify low resolution infrared image. The combination of reinforced VGG style network structure and global average pooling makes lower computational complexity and higher accuracy. The proposed method classify the synthesize image which have 9 class 3,723,328ea images made from OKTAL-SE tool. The reinforced VGG style network structure composed of 4 filters on input and 16 filters on output from max pooling layer shows about 34% lower computational complexity and about 2.4% higher accuracy then the first parameter minimized network structure made for embedded system composed of 8 filters on input and 8 filters on output from max pooling layer. Finally we get 96.1% accuracy model. Additionally we confirmed the about 31% lower inference lead time in ported C code.

• Journal of IKEEE
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• v.25 no.1
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• pp.88-94
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• 2021

Public-key cryptographic algorithms such as RSA and ECC, which are currently in use, have used mathematical problems that would take a long time to calculate with current computers for encryption. But those algorithms can be easily broken by the Shor algorithm using the quantum computer. Lattice-based cryptography is proposed as new public-key encryption for the post-quantum era. This cryptographic algorithm is performed in the Polynomial Ring, and polynomial multiplication requires the most processing time. Therefore, a hardware model module is needed to calculate polynomial multiplication faster. Number Theoretic Transform, which called NTT, is the FFT performed in the finite field. The logic verification was performed using HDL, and the proposed design at the transistor level using Hspice was compared and analyzed to see how much improvement in delay time and power consumption was achieved. In the proposed design, the average delay was improved by 30% and the power consumption was reduced by more than 8%.