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http://dx.doi.org/10.7471/ikeee.2021.25.1.88

Design of Efficient NTT-based Polynomial Multiplier  

Lee, SeungHo (School of Electronic & Electrical Eng. Hongik University)
Lee, DongChan (School of Electronic & Electrical Eng. Hongik University)
Kim, Yongmin (School of Electronic & Electrical Eng. Hongik University)
Publication Information
Journal of IKEEE / v.25, no.1, 2021 , pp. 88-94 More about this Journal
Abstract
Public-key cryptographic algorithms such as RSA and ECC, which are currently in use, have used mathematical problems that would take a long time to calculate with current computers for encryption. But those algorithms can be easily broken by the Shor algorithm using the quantum computer. Lattice-based cryptography is proposed as new public-key encryption for the post-quantum era. This cryptographic algorithm is performed in the Polynomial Ring, and polynomial multiplication requires the most processing time. Therefore, a hardware model module is needed to calculate polynomial multiplication faster. Number Theoretic Transform, which called NTT, is the FFT performed in the finite field. The logic verification was performed using HDL, and the proposed design at the transistor level using Hspice was compared and analyzed to see how much improvement in delay time and power consumption was achieved. In the proposed design, the average delay was improved by 30% and the power consumption was reduced by more than 8%.
Keywords
NTT; Polynomial Multiplication; Modular Arithmetic; Modular Subtraction Unit; HDL;
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1 C. P. Renteria-Mejia and J. Velasco-Medina, "Hardware Design of an NTT-based Polynomial Multiplier," in Proc. of the IX Southern Conference on Programmable Logic (SPL), pp.1-5, 2014. DOI: 10.1109/SPL.2014.7002209   DOI
2 A. C. Mert et al., "Design and Implementation of a Fast and Scalable NTT-Based Polynomial Multiplier Architecture," in Proc. of the Euromicro Conference on Digital System Design (DSD), pp.253-260, 2019. DOI: 10.1109/DSD.2019.00045   DOI
3 J. G. Proakis and D. G. Manolakis, Digital Signal Processing, 4th Edition, Prentice Hall, 2007.
4 A. C. Mert et al., "FPGA implementation of a run-time configurable NTT-based polynomial multiplication hardware," Microprocessors and Microsystems, vol.78, pp.103219, 2020. DOI: 10.1016/j.micpro.2020.103219   DOI
5 S. Vijayakumar and R. Korah, "Area and power efficient hybrid PTCSL MUX design," European Journal of Scientific Research, vol.83, no.1, pp.39-52, 2012.
6 M. Alioto and G. Palumbo, "Analysis and Comparison on Full Adder Block in Submicron Technology," IEEE Transactions on VLSI Systems, vol.10, no.6, pp.806-823, 2002. DOI: 10.1109/TVLSI.2002.808446   DOI
7 H. Nejatollahi, et al., "Post-Quantum Lattice-Based Cryptography Implementations: A Survey," ACM Computing Surveys, vol.51, no.6, pp.1-41, 2019. DOI: 10.1145/3292548   DOI
8 R. C. Agarwal and C. S. Burrus, "Number Theoretic Transforms to Implement Fast Digital Convolution," Proceedings of the IEEE, vol.63, no.4, pp.550-560, 1975. DOI: 10.1109/PROC.1975.9791   DOI
9 G. X. Yao, et al., "Recofigurable Number Theoretic Transform Architectures for Cryptographic Applications," in Proc. of the International Conference on Field-Programmable Technology, pp.308-311, 2010. DOI: 10.1109/FPT.2010.5681440   DOI
10 P. Longa and M. Naehrig, Cryptology and Network Security, Springer, Cham, 2016. DOI: 10.1007/978-3-319-48965-0   DOI