• Proceedings of the Korean Information Science Society Conference
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• 2007.10b
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• pp.264-268
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• 2007

연결선(interconnect) 사이의 간섭으로 발생하는 crosstalk 지연시간(delay)을 제거하기 위한 두 가지의 방법을 제안 한다. (1) 체계적인 코드를 생성해내는 방법으로 crosstalk 지연시간(delay) 유발 경우를 두 가지의 종류로 분류하여 각각에 대해 버스(bus) 비트 수의 증가에 따른 analytic 한 코드 생성 공식을 유도하였다; (2) 부-버스(sub-bus) 간에 발생하는 crosstalk 지연시간(delay)을 기존의 방법에 비해 보다 효율적으로 제거하는, 즉 추가적인 차단 라인 (또는 complement 비트 라인)를 감소시키는 방법을 제안 한다. 두 연구 결과는 연결선 상의 데이터 전송에 따른 신뢰성, 지연시간 및 전력 소모 증가를 유발하는 crosstalk를 차단하는 엔코딩 기법으로 유용하게 사용될 것으로 보인다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.56-65
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• 2001

This paper proposes an algorithm for the capacitance extraction of general 3-dimensional conductors in an ideal uniform dielectric that uses a high-order quadrature approximation method combined with the typical first-order collocation method to enhance the accuracy and adopts an efficient matrix-vector product algorithm for the model-order reduction to achieve efficiency. The proposed method enhances the accuracy using the quadrature method for interconnects containing corners and vias that concentrate the charge density. It also achieves the efficiency by reducing the model order using the fact that large parts of system matrices are of numerically low rank. This technique combines an SVD-based algorithm for the compression of rank-deficient matrices and Gram-Schmidt algorithm of a Krylov-subspace iterative technique for the rapid multiplication of matrices. It is shown through the performance evaluation procedure that the combination of these two techniques leads to a more efficient algorithm than Gaussian elimination or other standard iterative schemes within a given error tolerance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.37-44
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• 2006

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.22-33
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• 1999

In this paper, we propose a new multi-way circuit partitioning system that partition large circuits to progrmmable circuit board which consist of FPGAs and interconnect components. Here the routing topology among the chips are predetermined and the number of available interconnections are fixed. Since the given constraints are difficult to be satisfied by the previous partition method, we suggest a new multi-way partition method by target restriction that considers all the constraints for the given board. To speed up, we construct a multi-level cluster tree for hierarchical partitioning. Experimental results for several benchmarks show that the our partition method partition them by satisfying all the given constraints and it used up to 10 % fewer interconnections among the chips than the previous K-way partition method.

• Journal of the Korean Chemical Society
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• v.47 no.6
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• pp.659-662
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• 2003

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.77-83
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• 2004

Cross-talk noise which can occur between on-chip interconnects is significant factor which influence signal integrity. Therefore, this paper presents an analytical method for estimating maximum cross-talk noise. We consider inductance effect of interconnects and use arbitary ramp inputs to estimate noise magnitude exactly. Also, we have used a virtual source for the easy of analytically caculating maximum cross-talk noise from complex cross-talk noise model. The accuracy of the has been shown that be within 4.3 percent maximum relative error compared with the results of HSPICE simulation. Hence, this study can be utilized in various CAD tools for guaranteeing signal integrity.

• Journal of IKEEE
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• v.13 no.4
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• pp.50-56
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• 2009

This paper describes the design of image data transmitter for portable media device for Mobile Display Digital Interface standard. The transmitter uses connection lines to 6 to transmit QVGA image data. In this paper, the transmitter is using only 9 packets for image processing and a state-machine based design is adapted for packet processing. The design was verified using FPGA Xilinx virtex4-LX60. Data rate of the transmitter is 363Mbps with six connection lines. The transferring capability is 30 frame of 24bit RGB 500,000 pixel image data per second.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.6
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• pp.591-598
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• 2003

A novel transversal filter using triple-coupled-line directional couplers is proposed. Simple design method which uses sinc function for computing coupling coefficients of the proposed transversal filter are also introduced. The frequency characteristics of the proposed filter are seldom degraded by the connecting sections between the cascaded directional couplers while those of the conventional transversal filter are aggravated. Moreover, the less number of the connecting sections and the directional couplers is required in the proposed filter than fer the case of the conventional transversal filter having the same bandwidth. The performance of the proposed transversal filter is verified by measurement and the measured results are compared with the calculated results.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.766-780
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• 1996

This paper presents a mapping scheme for parallel processing using an accurate characterization of the communication overhead. A set of objective functions is formulated to evaluate the optimality of mapping a problem graph into a system graph. One of them is especially suitable for real-time applications of parallel processing. These objective functions are different from the conventional objective functions in that the edges in the problem graph are weighted and the actual distance rather than the nominal distance for the edges in the system graph is employed. This facilitates a more accurate qualification of the communication overhead. An efficient mapping scheme has been developed for the objective functions, where two levels of assignment optimization procedures are employed: initial assignment and pairwise exchange. The mapping scheme has been tested using the hypercube as a system graph.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.26-34
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• 1998

This paper presents a characterization method for faults of circuit patterns on MCM(Multichip Module) or PCB(Printed Circuit Board) substrates with electron beams of a SEM(Scanning Electron Microscope) by inducing voltage contrast on the signal line. The experimentation employes dual potential electron beams for the fault characterization of circuit patterns with a commercial SEM without modifying its structure. The testing procedure utilizes only one electron gun for the generation of dual potential electron beams by two different accelerating voltages, one for charging electron beam which introduces the yield of secondary electron $\delta$ < 1 and the other for reading beam which introduces $\delta$ > 1. Reading beam can read open's/short's of a specific net among many test nets, simultaneously discharging during the reading process for the next step, by removing its voltage contrast. The experimental results of testing the copper signal lines on glass-epoxy substrates showed that the state of open's/short's had generated the brightness contrast due to the voltage contrast on the surface of copper conductor line, when the net had charged with charging electron beams of 7KV accelerating voltages and then read with scanning reading electron beams of 2KV accelerating voltages in 10 seconds. The experimental results with Au pads of a IC die and Au plated Cu pads of BGA substrates provided the simple test method of circuit lines with 7KV charging electron beam and 2KV reading beam. Thus the characterization method showed that we can test open and short circuits of the net nondestructively by using dual potential electron beams with one SEM gun.