• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.12
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• pp.1062-1070
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• 2015

This paper presents an application of an optimal smoothing filter for moving target tracking problem based on measured noise source. In order to measure distance and velocity for the moving target, a beamforming method is applied to use the noise source by using microphone array. Also a Kalman filter and an optimal smoothing algorithm are adopted to improve accuracy of trajectory estimation by using a Singer target model. The simulation is conducted with a missile dynamics to verify performance of the optimal smoothing filter, and a model rocket is used for experiment environment to compare the trajectory estimation results between the beamforming, the Kalman filter, and the smoother. The Kalman filter results show better tracking performance than the beamforming technique, and the estimation results of the optimal smoother outperform the Kalman filter in terms of trajectory accuracy in the experiment results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.2
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• pp.32-45
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• 2000

This paper presents the analytic derivation of the SINR, when a linear array antenna is accommodated into the cellular CDMA basestation receiver, in relation to the two major performance effecting factors in beamforming(BF) applications, i. e., the direction selectivity, which refers to the narrowness of the mainbeam width, and the direction-of-arrival(DOA) estimation accuracy. The analytically derived results are compared with the operation simulation of the receiver realized with the several BF algorithms and their agreements are confirmed, consequently verifying the correctness of the analysis and the operation simulation. In order to investigate separately the effects of the errors occurring in the direction estimation and in the interference suppression, which are the two major functional components of general BF algorithms, both the algorithms of steering BF and the minimum- variance- distortionless-response(MVDR) BF are applied to the analysis. A signal model to reflect the spatially scattering phenomenon of the RF waves entering into the .:nay antenna, which directly affects on the accuracy of the BF algorithm's direction estimation, is also suggested in this paper and applied to the analysis and the operation simulation. It is confirmed from the results that the enhancement of the direction selectivity of the away antenna is not desirable in view of both the implementation economy and the BF algorithm's robustness to the erroneous factors. Such a trade-off characteristics is significant in the sense that it can be capitalized to obtain an economic means of BF implementation that does not severely deteriorate its performance while ensuring the robustness to the erroneous effects, consequently manifesting the significance of the analysis results of this paper that can be used as a design reference in developing BF algorithms to the cellular CDMA system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.51-60
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• 2005

The design of efficient cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. Especially, among the basic arithmetic over finite field, the rnultiplicative inversion is the most time consuming operation. In this paper, a fast inversion algerian in finite field $GF(2^m)$ with the standard basis representation is proposed. It is based on the Extended binary gcd algorithm (EBGA). The proposed algorithm executes about $18.8\%\;or\;45.9\%$ less iterations than EBGA or Montgomery inverse algorithm (MIA), respectively. In practical applications where the dimension of the field is large or may vary, systolic array sDucture becomes area-complexity and time-complexity costly or even impractical in previous algorithms. It is not suitable for low-weight and low-power systems, i.e., smartcard, the mobile phone. In this paper, we propose a new hardware architecture to apply an area-efficient and a synchronized inverter on low-complexity systems. It requires the number of addition and reduction operation less than previous architectures for computing the inverses in $GF(2^m)$ furthermore, the proposed inversion is applied over either prime or binary extension fields, more specially $GF(2^m)$ and GF(P) .

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.361-361
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• 2013

비냉각 적외선 검출소자는 빛이 전혀 없는 환경에서도 사물을 감지하는 열상장비의 핵심소자이다. 마이크로볼로미터 적외선 검출기는 상온에서 동작하며, 온도안정화를 위해 TEC를 장착하여 진공패키지로 조립된다. 패키지는 진공을 유지할 수 있도록 일반적으로 메탈로 제작되며, 단가 감소 및 생산성 증대를 위해 wafer level packaging 방법을 이용한다. 마이크로볼로미터의 특성은 패키지의 진공 변화에 매우 민감하다. 센서의 감도를 증가시키기 위해서는 진공환경을 유지해야 한다. 볼로미터 소자의 특성은 상압에서 열전도는 기판과 멤브레인 사이의 에어갭을 통해 열손실을 야기하므로 센서의 반응도가 현저히 줄어든다. 에어갭이 1 um 정도 되더라도 그 사이에 존재하는 열전도가 가능하므로 진공을 유지하여 열고립 상태를 증대시킬 수 있다. 이에 본 연구에서는 소자의 동작시 압력, 즉 진공도가 볼로미터 소자의 반응도 특성에 미치는 영향을 조사하였다. 마이크로볼로미터 소자는 $2{\times}8$ 어레이 형태로 제작하였으며, metal pad를 각 단위셀에 배치하였으며, 공통전극으로 한 개의 metal pad를 넣어 설계하였다. 흡수체로써 VOx를 사용하였으며, 열 고립구조를 위해 2.5 um 공명 흡수층의 floating 구조로 멤브레인을 형성하였다. 진공패키지는 메탈패키지를 제작하여 볼로미터 칩을 TEC 위에 장착하였으며, 신호의 감지를 위해 가변저항을 매칭시켰다. 반응도는 신호 대 잡음 값을 획득하여 소자에 도달하는 적외선 에너지에 대해 반응하는 값을 계산에 의해 얻어내는 것이다. 픽셀 크기는 $50{\times}50$ um이며, 패키지 조립 공정 후 온도변화에 따른 저항 측정을 통해 TCR 값을 얻었다. 이때 TCR은 약 -2.5%/K으로 나타났다. $2{\times}8$의 4개 단위소자에 대해 측정한 값은 균일하게 TCR 값이 나타났다. 광반응 특성은 볼로미터 단위소자에 대해서 먼저 고진공(5e-6 torr) 하에서 측정하였으며, 반응도는 25,000 V/W의 값을 나타내었고, 탐지도는 약 2e+8 $cmHz_{1/2}$/W로 나타났다. 패키지의 압력 조절을 위해 TMP 및 로터리 펌프를 이용하여 100 torr에서 1e-4 torr의 범위에서 압력조절 밸브를 이용하여 질소가스의 압력으로 진공도를 변화시켰다. 적외선 반응신호는 압력이 증가함에 따라 감소하였으며, 2e-1 torr의 압력에서 신호의 크기가 감소하기 시작하여 5 torr에서 반응도의 1/2 값을 나타냄을 알 수 있었다. 30 torr 이상에서는 신호가 잡음값 과거의 동일하여 신호대 잡음비가 1로 나타남을 알 수 있었다. 또한 진공도 변화에 대해, 흑체온도에 따른 반응도 및 탐지도의 특성을 조사한 결과를 발표한다. 반응도의 증가를 위해 진공도는 진공도는 1e-2 torr 이하의 압력을 유지해야 함을 본 실험을 통해 알 수 있었다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.48-57
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• 2020

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.