• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.59-66
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• 2004

This paper presents a novel fabrication process for a tapered hollow metallic microneedle array using backside exposure of SU-8, and analytic solutions of critical buckling of a tapered hollow microneedle. An SU-8 meta was formed on a Pyrex glass substrate and another SU-8 layer, which was spun on top of the SU-8 mesa, was exposed through the backside of the glass substrate. An array of SU-8 tapered pillar structures. with angles in the range of $3.1^{\circ}{\sim}5^{\circ}$ was formed on top of the SU-8 mesa. Conformal electrodeposition of metal was carried out followed by a mechanical polishing using a pianarizing polymeric layer. All organic layers were then removed to create a metallic hollow microneedle array with a fluidic reservoir on the backside. Both $200{\mu}m\;and\;400{\mu}m$ tall, 10 by 10 arrays of metallic microneedles with inner diameters of the tip in the range of $33.6{\sim}101\;{\mu}m$ and wall thickness of $10{\mu}m\;-\;20{\mu}m$ were fabricated. Analytic solutions of the critical buckling of arbitrary-angled truncated cone-shaped columns are also presented. It was found that a single $400{\mu}m$ tall hollow cylindrical microneedle made of electroplated nickel with a wall thickness of $20{\mu}m$, a tapered angle of $3.08^{\circ}$ and a tip inner diameter of $33.6{\mu}m$ has a critical buckling force of 1.8 N. This analytic solution can be used for square or rectangular cross-sectioned column structures with proper modifications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2369-2379
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• 2013

A CMOS x-ray line scan sensor which is used in both medical imaging and non-destructive diagnosis is designed. It has a pixel array of 512 columns ${\times}$ 4 rows and a built-in DC-DC converter. The pixel circuit is newly proposed to have three binning modes such as no binning, $2{\times}2$ binning, and $4{\times}4$ binning in order to select one of pixel sizes of $100{\mu}m$, $200{\mu}m$, and $400{\mu}m$. It is designed to output a fully differential image signal which is insensitive to power supply and input common mode noises. The layout size of the designed line scan sensor with a $0.18{\mu}m$ x-ray CMOS image sensor process is $51,304{\mu}m{\times}5,945{\mu}m$.

• Journal of the Korea Convergence Society
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• v.9 no.9
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• pp.183-189
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• 2018

This study deals with the design and development of imaging optics having 24mm focal length for MWIR ($3{\sim}5{\mu}m$) with two symmetrical lenses facing each other. We used CodeV in our optical design, and we performed the optimization process to have the resolution and angle of view satisfying the user's requirements. The materials of lenses were limited to two types, including KCIR035 with a refractive index of 1.7589, developed in Korea. The optical system designed in this way consists of two aspherical lenses made of KCIR035 material having the same shape and one spherical lens made of Si. Here, the arrangement of the two aspherical lenses is characterized by having a symmetrical structure facing each other. And this optical system has a resolution of MTF value of 0.35 or more at a line width of 20 lp / mm. Therefore, it is considered that this optical system has the capability to be applied to a thermal imaging camera using a $206{\times}156$ array MWIR detection device having a pixel size of $25{\mu}m$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.145-155
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.39 no.3
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• pp.218-229
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• 2003

A new biotelemetry method that the installation and the treatment of equipment is convenient and the instantaneously detailed location of the fish attached the pinger is able to track comparatively easily was developed. The receiving system in this biotelemetry method was advanced for track the detailed behavior of the fish by the miniature tracking pinger, because it was a burden to fish to add the pinger with the water temperature and the pressure sensor. By combining of the super short base line (SSBL) method to detect the direction of pinger and the pinger synchronizing method to measure the range from receiving transducer to pinger, the three dimensional locations of fish to the receiving transducer is gotten instantaneously. The receiving system is devised to realize the high precision or wide detection range by application of the basic design method for receiving system of biotelemetry developed by the present authors and the hydrophone array configuration. The measurement distance error in the pinger synchronizing method is minimized through the correction of which the deviation of transmission pluse period of pinger is caused by changing water temperature. A prototype system which is able to track the instantaneously detailed location of the fish by the SSBL and pinger synchronizing biotelemetry (SPB) method was produced.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.2
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• pp.9-22
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• 2004

This paper presents a parallel genetic algorithm for the Multi-disk data allocation problem an NP-complete problem. This problem is to find a method to distribute a Binary Cartesian Product File on disk-arrays to maximize parallel disk I/O accesses. A Sequential Genetic Algorithm(SGA), DAGA, has been proposed and showed the superiority to the other proposed methods, but it has been observed that DAGA consumes considerably lengthy simulation time. In this paper, a parallel version of DAGA(ParaDAGA) is proposed. The ParaDAGA is a 2-dimension torus-based Parallel Genetic Algorithm(PGA) and it is based on a distributed population structure. The ParaDAGA has been implemented on the parallel computer simulated on a single processor platform. Through the simulation, we study the impact of varying ParaDAGA parameters and compare the quality of solution derived by ParaDAGA and DAGA. Comparing the quality of solutions, ParaDAGA is superior to DAGA in all cases of configurations in less simulation time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1349-1359
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• 1998

In this paper, presented is the result of a digital implementation of a FM stereo composite signal generator. The chip utilizing DDFS(Direct Digital Frequency Synthesizer architecture is implemented using $1.0\mu\textrm{m}$ CMOS gate-array technology thereby replacing analog componentry. To verify the process of generating composite signals a conventional logic simulation method was used. The processed chip was mounted on an evaluation PCB to test and analyze to signals. According to the measurement result obtained by using a 12-bit DAC, the digital FM composite signal generator produces a 74DB spectrally pure signal over its entire tuning range, which is superior to that of analog counterpart by 14dB in it spectral reponse. And further enhancements of the spectral response is expected to be achieved by using a high resolution digital to analog converter, such as a 16-bit DAC. The resulting signals is superior to the signal of the analoy circuitry typically used, in major characteristics such as S/N ratios, accuracy, tuning stability, and signal seperation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.132-137
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• 2003

This performance is motivated to develop a tracking antenna system for receive the satellite broadcasting signal in the coast sailing ship. Therefore, this system is made to small size, light weight and simple operation which is must to low cost system for popularization of small size ship and adaptive possibilities with useful on a ship in the coast using 1 axis Az-mount. The antenna mount structure is a compact size and easy operation to the Az-axis type which is operated by step motor. The antenna unit is a domestic made plate type of patch array and ship's moving detection is using the gyro sensor for ship's moving control. We are designed to algorithm, which walking is abreast for step track and ship's moving compensation. Ship's moving compensation is adapted to the closed loop control method by detection from gyro sensor. This system is consisted of micro processor, ADC, comparative amplifier, step motor driver, mount mechanism and algorithm. We have analysised the tracking performance of prototype on sailing ship board.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.3
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• pp.238-243
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• 2008

Several experimental techniques for identifying the noise sources distributed over a moving vehicle have been developed recently and are used to design a low noise vehicle. The beamforming method, which uses phase information between several microphones to localize the source position, is proved to be one of the promising techniques applicable even under complicated test environments. In this study a beamforming algorithm is developed and applied to measure the dominant noise sources on a passenger car passing by. Unlike the acoustic signals from a stationary noise source, the sound generated from a moving source is distorted due to the Doppler effects. The information about the speed and relative position of the vehicle are used to eliminate the Doppler effects from the measured acoustic signal by using a de-Dopplerization algorithm. The noise generated from a moving vehicle can be grouped in many ways, however, tire noise and the noise generated from the engine are distinguishable at the speeds being tested.