• Journal of Advanced Navigation Technology
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• v.21 no.5
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• pp.466-471
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• 2017

SOTM is a device for the satellite communication on the move. Many studies are conducted on microstrip, waveguide and array antenna for the low profile of the SOTM's antenna. But those antennas have a problem that is difficult to adjust the polarization, and for that reason we have studied the parabolic antenna structure. The general form of parabolic reflector structure is circular, but we used cut-off shape reflector by cutting the upper and lower reflector for low profile antenna. Accordingly, this results in the decrease of reflector area which causes reduced gain and G/T ratio. In order to solve this problem, we have transformed and designed the sub reflector for improving the efficiency and gain of the cut- off shape parabolic antenna.

• Journal of Korean Association for Spatial Structures
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• v.10 no.1
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• pp.67-74
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• 2010

This paper focuses on steel arrays regarding the application of PV system for solar power system, a renewable energy in steel structure stadium that will be built in Korea, by foreign case study. 20 cases of Steel Structure Stadiums applying PV system after 1990 were selected as the main subjects. The 20 cases of Steel Structure Stadiums were categorized by rail systems that were installed to fix PV module. As the result, linear clamping and roof-integrated type among cross rails were 28% of the whole, followed by 17% of rail-fixed type and 11% of module group-fixed type among vertical-fixed types. In addition, linear clamping and roof-integrated type among cross rails were applied in the inside of the stadium while the outside and other parts of stadiums used angle bracket to fix PV module.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.1-7
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• 2023

The ability of 3D/4D printing technology to create arbitrary 3D structures provides a greater degree of freedom in the design of printed structures. This capability has influenced the field of electronics and biomedical applications by enabling the trends of device miniaturization, customization, and personalization. Here, the current state-of-the-art knowledge of 3D printed electronics and biomedical applications with the unique and unusual properties enabled by 3D/4D printing is reviewed. Specifically, the review encompasses emerging areas involving recyclable and degradable electronics, metamaterial-based pressure sensor, fully printed portable photodetector, biocompatible and high-strength teeth, bioinspired microneedle, and transformable tube array for 3D cell culture and histology.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.22-26
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• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

• Journal of the Korean Vacuum Society
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• v.18 no.3
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• pp.186-196
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• 2009

Since it is difficult to extract a high flux ion beam directly at an energy of hyperthermal range ($1{\sim}100\;eV$), especially, lower than 50 eV, the ions should be neutralized into neutral particles and extracted as a neutral beam. A plasma source required to generate and efficiently transport high flux hyperthermal neutral beams should be easily scaled up and produce a high ion density (${\ge}10^{11}\;cm^{-3}$) even at a low working pressure (${\le}$ 0.3 mTorr). It is suggested that the required plasma source can be realized by Electron Cyclotron Resonance (ECR) plasmas with diverse magnetic field configurations of permanent magnets such as a planar ECR plasma source with magnetron field configuration and cylindrical one with axial magnetic fields produced by permanent magnet arrays around chamber wall. In both case of the ECR sources, the electron confinement is based on the simple mirror field structure and efficiently enhanced by electron drifts for producing the high density plasma even at the low pressure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.51-60
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• 2005

The design of efficient cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. Especially, among the basic arithmetic over finite field, the rnultiplicative inversion is the most time consuming operation. In this paper, a fast inversion algerian in finite field $GF(2^m)$ with the standard basis representation is proposed. It is based on the Extended binary gcd algorithm (EBGA). The proposed algorithm executes about $18.8\%\;or\;45.9\%$ less iterations than EBGA or Montgomery inverse algorithm (MIA), respectively. In practical applications where the dimension of the field is large or may vary, systolic array sDucture becomes area-complexity and time-complexity costly or even impractical in previous algorithms. It is not suitable for low-weight and low-power systems, i.e., smartcard, the mobile phone. In this paper, we propose a new hardware architecture to apply an area-efficient and a synchronized inverter on low-complexity systems. It requires the number of addition and reduction operation less than previous architectures for computing the inverses in $GF(2^m)$ furthermore, the proposed inversion is applied over either prime or binary extension fields, more specially $GF(2^m)$ and GF(P) .

• Journal of the Microelectronics and Packaging Society
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• v.27 no.4
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• pp.55-60
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• 2020

The PERC photovoltaic (PV) modules installed in PV power plant are still reports potential-induced degradation (PID) degradation due to high voltage potential differences. This is because Na+ ions in the cover glass of PV modules go through the encapsulant (EVA) and transferred to the surface of solar cells. As positive charges are accumulated at the ARC (SiOx/SiNx) interface where many defects are distributed, shunt-resistance (Rsh) is reduced. As a result, the leakage current is increased, and decrease in solar cell's power output. In this study, to prevent of this phenomenon, a Moth-eye nanostructure was deposited on the rear surface of an optical film using Nano-Imprint Lithography method, and a solar mini-module was constructed by inserting it between the cover glass and the EVA. To analyze the PID phenomenon, a cell-level PID acceleration test based on IEC 62804-1 standard was conducted. Also analyzed power output (Pmax), efficiency, and shunt resistance through Light I-V and Dark I-V. As a result, conventional solar cells were decreased by 6.3% from the initial efficiency of 19.76%, but the improved solar cells with the Moth-eye nanostructured optical film only decreased 0.6%, thereby preventing the PID phenomenon. As of Moth-eye nanostructured optical film, the transmittance was improved by 4%, and the solar module output was improved by 2.5%.