• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1471-1479
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• 2017

This paper describes a design of RSA public-key cryptography processor supporting key length of 2,048 bits. A modular multiplier that is core arithmetic function in RSA cryptography was designed using word-based Montgomery multiplication algorithm, and a modular exponentiation was implemented by using Left-to-Right (LR) binary exponentiation algorithm. A computation of a modular multiplication takes 8,386 clock cycles, and RSA encryption and decryption requires 185,724 and 25,561,076 clock cycles, respectively. The RSA processor was verified by FPGA implementation using Virtex5 device. The RSA cryptographic processor synthesized with 100 MHz clock frequency using a 0.18 um CMOS cell library occupies 12,540 gate equivalents (GEs) and 12 kbits memory. It was estimated that the RSA processor can operate up to 165 MHz, and the estimated time for RSA encryption and decryption operations are 1.12 ms and 154.91 ms, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1401-1410
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• 2017

Cryptographic synchronization which synchronizes internal state of cryptographic algorithm and ciphertext stream between an encryptor and a decryptor affects the quality of secure communication. If there happens a synchronization loss between a transmitter and a receiver in a secure communication, the output of the receiver is unintelligible until resynchronization is made. Especially, in the secure communication on a wireless channel with high BER, synchronization performance can dominate its quality. In this paper, we proposed a novel and noise robust synchronization signal generation method as well as its detection algorithm. We generated a synchronization signal in the form of a masking structure based on the maximal length sequence, and developed a detection algorithm using a correlation property of the maximal length sequence. Experimental results have demonstrated that the proposed synchronization signal outperforms the conventional concatenated type synchronization signal in a noisy environment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.163-165
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• 2018

GF(p)상 타원곡선 암호(ECC)와 RSA를 단일 하드웨어로 통합하여 구현한 공개키 암호 프로세서를 설계하였다. 설계된 EC-RSA 공개키 암호 프로세서는 NIST 표준에 정의된 소수체 상의 224-비트 타원 곡선 P-224와 2048-비트 키 길이의 RSA를 지원한다. ECC와 RSA가 갖는 연산의 공통점을 기반으로 워드기반 몽고메리 곱셈기와 메모리 블록을 효율적으로 결합하여 최적화된 데이터 패스 구조를 적용하였다. EC-RSA 공개키 암호 프로세서는 Modelsim을 이용한 기능검증을 통하여 정상동작을 확인하였으며, $0.18{\mu}m$ CMOS 셀 라이브러리로 합성한 결과 11,779 GEs와 14-Kbit RAM의 경량 하드웨어로 구현되었다. EC-RSA 공개키 암호 프로세서는 최대 동작주파수 133 MHz이며, ECC 연산에는 867,746 클록주기가 소요되며, RSA 복호화 연산에는 26,149,013 클록주기가 소요된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1589-1596
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• 2017

In synchronous secure communications, a synchronization signal is transmitted over the same channel where ciphertext is transmitted for cryptographic synchronization between an encryptor and a decryptor, so, it causes data rate lowering and transmission delay for plain communication. Especially, in poor environments such as wireless channels and so on, since secure communications require a periodic resynchronization protocol, synchronization signal transmission method can dominate its quality. In this paper, we proposed a new synchronization signal transmission method without additional bandwidth as well as resynchronization protocol based on it. We embeded a synchronization signal as a watermark in a transmission image and restored it from a detected watermark in the decryptor. Experimental results of image have demonstrated that the proposed synchronization signal transmission method using watermarking is efficient in transmission rate and can support reliable synchronization detection.

• Journal of Convergence for Information Technology
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• v.9 no.1
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• pp.142-150
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• 2019

This study is a file management security system that encrypts and decrypts computer and cloud data by using Bluetooth based cryptographic module. It is a necessary solution in terms of abuse of personal information and protection of social and national information. We developed H/W and S/W for SFMS(: Safe File Management Security) related Bluetooth module in cloud environment and implemented firmware development, encryption key generation and issuance, client program for system mobile and key management system. In the terminal internal encryption and decryption, SFMS was developed to ensure high security that the hacking itself is not possible because key values exist separately for each file.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.39-44
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• 2009

The advance of communication and networking technology enables high bandwidth multimedia data transmission. The development of high performance compression technology such as H.264 also encourages high quality video and audio data transmission. The trend requires efficient protection system for digital media rights. We propose an efficient digital media protection system using elliptic curve cryptography. Only key parameters are encrypted to reduce the burden of complex encryption and decryption in the proposed system, and the digital media are not played back or the quality is degraded if the encrypted information is missing. We need a playback system with an ECC processor to implement the proposed system. We implement an H.264 decoding system with a configurable ECC processor to verify the proposed protection system We verify that the H.264 movie is not decoded without the decrypted information.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1609-1617
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• 2019

Described in this paper is a design of hardware accelerator for implementing public-key cryptographic protocols (PKCPs) based on Elliptic Curve Cryptography (ECC) and RSA. It supports five elliptic curves (ECs) over GF(p) and three key lengths of RSA that are defined by NIST standard. It was designed to support four point operations over ECs and six modular arithmetic operations, making it suitable for hardware implementation of ECC- and RSA-based PKCPs. In order to achieve small-area implementation, a finite field arithmetic circuit was designed with 32-bit data-path, and it adopted word-based Montgomery multiplication algorithm, the Jacobian coordinate system for EC point operations, and the Fermat's little theorem for modular multiplicative inverse. The hardware operation was verified with FPGA device by implementing EC-DH key exchange protocol and RSA operations. It occupied 20,800 gate equivalents and 28 kbits of RAM at 50 MHz clock frequency with 180-nm CMOS cell library, and 1,503 slices and 2 BRAMs in Virtex-5 FPGA device.

• Transactions on Semiconductor Engineering
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• v.1 no.1
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• pp.1-8
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• 2023

This paper presents the design and implementation of Crystals-Kyber, a next-generation postquantum cryptography, as a hardware accelerator on an FPGA using High-Level Synthesis (HLS). We optimized the Crystals-Kyber algorithm using various directives provided by Vitis HLS, configured the AXI interface, and designed a hardware accelerator that can be implemented on an FPGA. Then, we used Vivado tool to design the IP block and implement it on the ZYNQ ZCU106 FPGA. Finally, the video was recorded and H.264 compressed with Python code in the PYNQ framework, and the video encryption and decryption were accelerated using Crystals-Kyber hardware accelerator implemented on the FPGA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.67-74
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• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• The Journal of the Korea Contents Association
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• v.1 no.1
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• pp.74-82
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• 2001

Visual cryptography made it possible to decrypt the Information encrypted by thresholding scheme not with digital system but with human vision system. This method, however, has some limit in it because of the rack of resolution in both the spatial and amplitude domain. Optical visual cryptography, which used laser system instead of human eyesight, was proposed by conjunction of the optical theory with the cryptography. However, it also had some difficulties because it did not overcome the existing problem of visual cryptography completely. The problem occurred in the process of transferring data processing system from visual to optics. Therefore, it is appropriate to approach these problems in terms of optics. In this paper, we analysis, in the aspect of frequency, the security characteristics and the noise level occurred in the process of optical visual encryption.