• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.46.2-46.2
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• 2010

For use of superstrate thin-film solar cells, surface texture of the transparent conductive oxide (TCO) has been used to enhance short-circuit currents by increasing light trapping into the cell. ZnO:Al films were deposited by using DC magnetron sputtering on glass substrates with ceramic (ZnO:$Al_2O_3$) target. The as-deposited TCO before texturing exhibited high transparencies (T > 85% for visible light including all reflection losses) and excellent electrical properties ($r=3-6{\times}10^{-4}{\Omega}.cm$). The optical and electrical properties of the TCO are influenced by the texturing conditions such as not only etchant dilutions but also etching time. We obtained the haze value of 14-16 resulting in increase in light trapping and short-circuit currents also.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.131.2-131.2
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• 2015

마이크로웨이브를 이용한 플라즈마는 효율적인 전자가열이 가능하며, 낮은 이온에너지를 가지는 고밀도 플라즈마를 생성시킬 수 있다는 장점이 있다. 최근 산화물 반도체 및 대화면 디스플레이 장치내 소자의 보호막 증착용으로 저온 PECVD (Plasma Enhanced Chemical Vapor Deposition) 공정 및 장치의 필요성에 따라 마이크로웨이브를 이용한 PECVD 장치가 주목 받고 있다. 본 연구에서는 실리콘 나이트라이드 공정 장치 개발을 위한 2차원 시뮬레이션 모델을 완성하였다. Global modeling을 이용하여 확보한 Chemical reaction data에 대한 검증을 하였다. Maxwell's equation, continuity equation, electromagnetic wave equation 등을 이용하여 Microwave의 파워 및 압력에 따른 전자 밀도, 전자 온도등의 플라즈마 변수의 변화를 관찰하였다. 또한 Navier Stokes equation을 추가하여 챔버 내의 Gas flow의 흐름을 고려한 시뮬레이션을 진행하여 분석하였다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.8
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• pp.365-370
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• 2001

We have proposed and fabricated a new poly-Si TFT employing air-cavities at the edges of gate oxide in order to reduce the vertical electric field induced near the drain due to low dielectric constant of air. Air-cavity has been successfully fabricated by employing the wet etching of gate oxide and APCVD (Atmospheric pressure chemical vapor deposition) oxide deposition. Our experimental results show that the leakage current of the proposed TFT is considerably reduced by the factor of 10 and threshold voltage shift under high gate bias is also reduced because the carrier injection into gate insulator over the drain depletion region is suppressed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.334-338
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• 2006

Poly silicon TFT requires high quality dielectric film; conventional method of growing silicon dioxide needs highly hazardous chemicals such as silane. We have grown high quality dielectric film of silicon dioxide using non-hazardous chemical such as TFOS and ozone as reaction gases by APCVD. The films grown were characterized through C-V curves of MOS structures. Conventional APCVD requires high temperature processing where as in the process of current study, we developed a low temperature process. Interface trap density was substantially decreased in the silicon surface coated with the silicon dioxide film after annealing in nitrogen ambient. The interface with such low trap density could be used for poly silicon TFT fabrication with cheaper cost and potentially less hazards.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.371-371
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• 2010

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the MEMS implementation with nano structure. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41{\AA}$, which have the gate area $10^{-3}cm^2$. The stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.17-20
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• 2002

This study has been investigated that traps generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The charge state of the traps can easily be changed by application of low voltages after the stress high voltage. These trap generation involve either electron impact ionization processes or high field generation processes. It determined to the relative traps locations inside the oxides ranges from 113.4A to 814A with capacitor areas of 10$^{-3}$ $\textrm{cm}^2$ The oxide charge state of traps generated by the stress high voltage contain either a positive or negative charge.

• Proceedings of the Korean Vacuum Society Conference
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• 1997.02a
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• pp.68-68
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• 1997

pp-typpe Si(100) Metal-Oxide-Semiconductor(MOS) 구조에서 산화막과 실리콘 사이의 계면상태 및 결함상태를 Isothermal Cappacitance Transient Sppectroscoppy (ICTS)방법을 이용하여 조사하였다. 특히 pplasma를 이용한 수소화이후 이 구조의 계면상태와 결함상태의 변화를 연구하였다. 상온에서 수소화한 MOS 구조의 경우 결함 상태의 농도가 급속히 감소함을 알 수 있었다. 이 구조에서 나타나는 모든 결함상태의 농도가 급격하게 감소하는 반면에, 수소화에 의한 새로운 깊은준이 결함상태도 관측되었다. 이 깊은 준위 결함 상태는 가전자대 위로부터 0.38eV 위치에 존재하였으며, 열적으로 안정된 결함상태로서, 해리에너지가 2.15$\pm$0.05 eV 이었다. 수소화이후 나타난 이 결함상태는 수소 플라즈마에 의해 구속된 Si원자가 수소원자와 결합하여 outdiffusion함으로 나타난 결함상태로 생각된다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.3
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• pp.134-142
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• 1995

We discovered that each distinct shape of the roof-shaped peaks of (111) facets, which are generated on (110) cross-section of the directly bonded (100) silicon wafer pairs after KOH etching, can be mapped to one of three conditions of the interfacial oxide existing at the bonding interface as follows. That is, thick solid line can be mapped to stabilization, thin solid line to disintegration, and thin broken line to spheroidization. also we confirmed that most of the interfacial oxides of a well-aligned wafer pairs were disintegrated and spheroidized through high-temperature annealing process above 900$^{\circ}$C while the oxide was stabilized persistently when two wafers are bonded rotationally around their common axis perpendicular to the wafer planes.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1816-1818
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• 1996

A micro-size nonthermal plasma generator, using a $SiO_2$ film as a dielectric barrier, has been studied experimentally for a high frequency ac voltage in 2LPM oxygen gas fed. The $SiO_2$ film as a micro-size dielectric barrier was made by the wet oxidation of n-type Si wafer($220[{\mu}mt]$). It can be generated ozone, as a nonthermal plasma intensity parameter, at very low level of applied voltage about 1[kV] by using the micro-size dielectric barrier. As a result, in case that have no air gap spacing i.e. surface discharge case shows relatively higher ozone concentration rather than that case of the micro-airgap spacing.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.296-298
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• 1997

The performance of thin film pressure sensors with polyimide and silicon oxide as a insulating layer between the stainless steel diaphragm and the Cu-Ni strain gauges is presented. The polyimide was spun on the stainless steel diaphragm and cured in an oven. The silicon oxide was deposited by rf sputtering. The thin film pressure sensor with silicon oxide as a insulating layer showed a better nonlinearity and a lower hysteresis.