• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.1-6
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• 2008

A compact analytical model of the threshold voltage for long-channel Asymmetric Double-Gate(ADG) MOSFET is presented. In contrast to the previous models, channel doping and carrier quantization are taken into account. A more compact model is derived by utilizing the potential distribution linearity characteristic of silicon film at threshold. The accuracy of the model is verified by comparisons with numerical simulations for various silicon film thickness, channel doping concentration and oxide thickness.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.401-401
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• 2011

태양전지 제작에 있어서 에미터층의 최적화를 위해 POCl 도핑시 에미터층의 면저항 가변에 중요한 파라미터인 온도와 가스비를 변화하여 실험을 진행하였다. 본 실험에 사용될 최초 기판은 두께가 200${\pm}$5 ${\mu}m$, 비저항이 0.5~0.3 ${\Omega}{\cdot}cm$의 P-type(100) 실리콘 기판을 사용하였으며 먼저 POCl3양과 deposition 시간 그리고 산소와 질소의 양을 고정시키고 온도에 따른 에미터 면저항 변화를 알아보았다. 온도는 830, 840, 850, 860, 870, 880$^{\circ}C$로 가변시켰으며 공정온도가 높아질수록 면저항 값이 낮아짐을 알 수 있었다. 균일도는 낮은 온도에서는 다소 좋지 않았지만 온도가 높아질수록 점차 좋아졌으며 870$^{\circ}C$ 이상에서는 거의 균일한 값을 얻을 수 있었다. 한편, 이번에는 공정온도를 고정하고 산소와 POCl3 가스량의 변화에 따른 면저항 특성과 균일도를 알아보았다. 가스비와 압력 그리고 위치별 면저항 특성에 대해서 알아보았고 부분압이 증가함으로 반응로 내의 O2의 양이 증가함을 알 수 있었다. 증가한 O2는 도핑과정에서 산화막을 더 두껍게 형성하게 하며 높은 면저항 값을 가져오게 하였다. 즉, 충분한 가스량의 주입으로 도핑시 균일도를 향상시킬 수 있었다. 이와 같이 부분압이 증가함에 따라 면저항의 증가와 균일도의 향상을 가져왔다.

• Proceedings of the KAIS Fall Conference
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• 2006.05a
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• pp.339-343
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• 2006

전기발광소자는 바이폴라소자로서 전자와 정공의 주입, 이동 및 재결합에 의하여 발광한다. 소자에 사용되는 발광층의 대표 물질인 $Alq_3$를 한층(single layer)만 사용하고 정공의 주입을 도와주기위하여 폴리테트라플로로에틸렌(테플론)층을 얇게 증착하여 두께 변화에 따른 소자의 전기적 발광 특성을 측정하였다. 테플론은 좋은 부도체 폴리머로서 정공 터널링 전류가 두께 2 nm에서 가장 크게 증가하였으며 효율도 최대에 이르렀다. 주사전자현미경을 이용하여 실리콘 기판에 증착시킨 테플론 박막의 조직을 조사한 결과 두꺼워 질수록 라멜라(섬유조직)가 발달함을 알 수 있었다. 전자 주입을 도와주는 터널링층으로서 알루미늄산화막을 $Alq_3$ 위에 3 ${\AA}$ 증착한 결과 전류와 효율이 더 증가하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.996-1000
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• 2005

Experimental results are presented for the degradation of 3 nm-thick gate oxide $(SiO_2)$ under both Negative-bias Temperature Instability (NBTI) and Hot-carrier-induced (HCI) stresses using P and NMOSFETS, The devices are annealed with hydrogen or deuterium gas at high-pressure $(1\~5\;atm.)$ to introduce higher concentration in the gate oxide. Both interface trap and oxide bulk trap are found to dominate the reliability of gate oxide during electrical stress. The degradation mechanism depends on the condition of electrical stress that could change the location of damage area in the gate oxide. It was found the trap generation in the gate oxide film is mainly related to the breakage of Si-H bonds in the interface or the bulk area. We suggest that deuterium bonds in $SiO_2$ film are effective in suppressing the generation of traps related to the energetic hot carriers.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.32 no.10
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• pp.800-809
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• 2008

Scanning Thermal Microscope (SThM) is the tool that can map out temperature or the thermal property distribution with the highest spatial resolution. Since the local temperature or the thermal property of samples is measured from the extremely small heat transferred through the nanoscale tip-sample contact, improving the sensitivity of SThM probe has always been the key issue. In this study, we develop a new design and fabrication process of SThM probe to improve the sensitivity. The fabrication process is optimized so that cantilevers and tips are made of thermally grown silicon dioxide, which has the lowest thermal conductivity among the materials used in MEMS. The new design allows much higher tip so that heat transfer through the air gap between the sample-probe is reduced further. The position of a reflector is located as far away as possible to minimize the thermal perturbation due to the laser. These full $SiO_2$ SThM probes have much higher sensitivity than that of previous ones.

• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.13-16
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• 2012

Zinc oxide (ZnO) films were deposited by an RF magnetron sputtering system with the RF power of 200W and 300W and flow rate of oxygen gases of 20 and 30 sccm, in order to research the growth of ZnO on carbon doped silicon oxide (SiOC) thin film. The reflectance of SiOC film on Si film deposited by the sputtering decreased with increasing the oxygen flow rate in the range of long wavelength. In comparison between ZnO/Si and ZnO/SiOC/Si thin film, the reflectance of ZnO/SiOC/Si film was inversed that of ZnO/Si film in the rage of 200~1000 nm. The transmittance of ZnO film increased with increasing the oxygen gas flow rate because of the transition from conduction band to oxygen interstitial band due to the oxygen interstitial (Oi) sites. The low reflectance and the high transmittance of ZnO film was suitable properties to use for the front electrode in the display or solar cell.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.252-259
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• 1990

This paper present new scheme for a Side Wall Masked Isolation(SWAMI) technology which take all the advatages provided by conventional LOCOS process. A new SWAMI process incorporates a sloped sidewall by reactive ion etch and a layer of thin nitride around the side walls such that both intrinsic nitride stress and volume expansion induced stress are greatly reduced. As a fabricate results, a defect-free fully recessed zero bird's beak local oxidation process can be realized by the sloped wall anisotropic oxide isolation. No additional masking step is required. The leakage current of PN diodes of this process were reduced than PN diode of conventional LOCOS process. On the other hand, the edge junction part was larger than the flat juction part in the density of leakage current.

• Electrical & Electronic Materials
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• v.7 no.3
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• pp.231-235
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• 1994

The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.131-136
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• 2000

We have investigated the slurry induced metallic contaminations of undoped and doped silicate oxides surface on CMP cleaning process. The metallic contaminations by CMP slurry were evaluated in four different oxide films, such as plasma enhanced tetra-ethyl-orthyo-silicate glass(PE-TEOS), O3 boro-phos-pho-silicate glass(O3-BPSG), PE-BPSG, and phospho-silicate glass(PSG). All films were polished with KOH-based slurry prior to entering the post-CMP cleaner. The Total X-Ray fluorescence(TXRF) measurements showed that all oxide surfaces are heavily contaminated by potassium and calcium during polishing which is due to a CMP slurry. The polished O3-BPSG films presented higher potassium and calcium contaminations compared to PE-TEOS because of a mobile ions gettering ability of phosphorus. For PSG oxides, the slurry induced mobile ion contamination increased with an increase of phosphorus contents. In addition, the polishing removal rate of PSG oxides had a linear relationship as a function of phosphorus contents.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.3-6
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• 2003

This paper describes the interface stability of Ta-Mo alloy metal on $SiO_2$ Alloy was formed by co-sputtering method, and the alloy composition was varied by controlling Ta and Mo sputtering power. When the atomic composition of Ta was about 91%, the measured work function was 4.2eV that is suitable for NMOS gate. To identify interface stability between Ta-Mo alloy metal and $SiO_2$, C-V, FE-SEM(Field Emission-SEM), and XRD(X-ray diffraction) were performed on the samples annealed with rapid thermal processor between $600^{\circ}C$ and $900^{\circ}C$. Even after $900^{\circ}C$ rapid thermal annealing, excellent interface stability and electrical properties were observed. Also, thermodynamic analysis was studied to compare with experimental results.