• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.39-45
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• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1983-1993
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• 1993

A power-reduction technique for full-flash A/D converters is proposed. As the resolution of a full-flash A/D converter increases linearly, the number of comparators increases exponentially. The power dissipation is generally larger than other A/D converter architectures because there are many comparators, and they are operating continuously. In this proposed architecture, only a selected number of conmarators are made to operate instead of activating all the comparators of the full-flash A/D convertor. To determine whichcomparators should be activated, voltage levelfider circuits are used. A new clock driver is developed to suppress the dynamic glitch noise which is fed back into the input stage of the comparator. By using this clock driver, the glitch noise in the current source is reduced to one fourth of that when the typical clock signal is applied. The proposed architecture has been implemented with 1.2 m 5GHz BiCMOS technology. The maximum conversion speed is 350Msamples/s. and dissipates only 900mW.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.46 no.3
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• pp.251-256
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• 2018

In the case of a radar repeater that used for the trajectory tracking of a high-speed aircraft, it emits pulses of short width. For phase displacement of these signals a branch type phase shifter is used. The phase on the transmission line is changed by utilizing the variable reactance at the end of the displacement branch transmission line. Further, it is easy to control the high output signal, and there is an advantage that the insertion loss is not large even when the reactance fails. In this paper, we will discuss the fabrication test results of a 400 W class phase shifter that sequentially displaces the phase at $0^{\circ}$, $30^{\circ}$, $60^{\circ}$, $90^{\circ}$.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.251-254
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• 1998

초음파 수신 신호의 공진주파수 변화를 이용한 온도 측정법에서 협대역 변환기를 사용한 초음파 온도측정이 가능함을 보여준다. 그리고 이를 위하여 공진주파수 변화와 온도변화간의 비례상수를 변화시켰다. 기존의 측정법은 온도변화와 기본주파수 변화와의 관계를 비례상수로 정의하였기 때문에, 최소한 3개 이상의 하모닉을 포함하는 광대역 변환기가 필요하였다. 하지만 협대역 변환기를 이용한 온도측정법에서는 비례상수를 주파수 변화비와 온도변화간의 관계로 나타내기 때문에 한 성분의 하모닉만을 측정하여도 온도측정이 가능하게 된다.

• Korean Journal of Optics and Photonics
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• v.19 no.1
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• pp.60-67
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• 2008

An all-optical 4-bit Gray code to binary coded decimal (BCD) converter by means of commercially available numerical analysis tool (VPI) was demonstrated, for the first time to our knowledge. Circuit design approach was modified appropriately in order to fit the electrical method on an all-optical logic circuit based on a cross gain modulation (XGM) process so that signal degradation due to the non-ideal optical logic gates can be minimized. Without regenerations, Q-factor of around 4 was obtained for the most severely degraded output bit (least significant bit-LSB) with 2.5 Gbps clean input signals having 20 dB extinction ratio. While modifying the two-level simplification method and Karnaugh map method to design a Gray code to BCD converter, a general design concept was also founded (one-level simplification) in this research, not only for the Gray code to BCD converter but also for any general applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2628-2635
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• 2010

This paper analyzes the detection probability of FMCW (Frequency Modulated Continuous Wave) radar based on Doppler frequency and analog-digital converter bit and designs and implements signal processing part of FMCW radar. For performance evaluation, the FMCW radar system consists of a transmitted part and a received part and uses AWGN channel. The system model is verified through analysis and simulation. Frequency offset occurs in the received part caused by the mismatching between the received signal and the reference signal. In case of Doppler frequency less than about 38KHz, performance degradation of detection does not occur in FMCW radar with 75cm resolution The analog-digital converter needs at least 6 bit in order not to degrade the detection probability. And, we design and implement digital signal processing part based on DDS chip of digital transmitted signal generator for FMCW radar.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.3
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• pp.165-169
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• 2008

Analog-to-Digital converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental converters provide a solution for such measurement applications, as they retain most of the advantages of conventional ${\Delta}{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. Most of the previous research on incremental converters was for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth ac signals is discussed. A design methodology to optimize the signal-to-quantization+thermal noise ratio of multiplexed IDC is presented. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1349-1359
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• 1998

In this paper, presented is the result of a digital implementation of a FM stereo composite signal generator. The chip utilizing DDFS(Direct Digital Frequency Synthesizer architecture is implemented using $1.0\mu\textrm{m}$ CMOS gate-array technology thereby replacing analog componentry. To verify the process of generating composite signals a conventional logic simulation method was used. The processed chip was mounted on an evaluation PCB to test and analyze to signals. According to the measurement result obtained by using a 12-bit DAC, the digital FM composite signal generator produces a 74DB spectrally pure signal over its entire tuning range, which is superior to that of analog counterpart by 14dB in it spectral reponse. And further enhancements of the spectral response is expected to be achieved by using a high resolution digital to analog converter, such as a 16-bit DAC. The resulting signals is superior to the signal of the analoy circuitry typically used, in major characteristics such as S/N ratios, accuracy, tuning stability, and signal seperation.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.18-26
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• 2015

In this paper, we studied the method for analyzing and estimating the parameters that induce I/Q imbalance in the repeater using direct conversion RF. In repeater, amplitude, phase, and filter mismatch are generated in the receiving-end which converts RF signal to baseband signal. And amplitude and phase mismatch are generated in the transmitting-end which converts baseband signal to RF signal. Accordingly, we modeled the parameters that cause I/Q imbalance in the structure of the repeater in order, and proposed a feedback test structure from the transmitting-end to the receiving-end for estimating the corresponding parameters. By comparing the test transmitting signal and received signal, it is possible to estimate the I/Q imbalance parameters which occurred from mixed components of real and imaginary part. And it was confirmed that I/Q imbalance phenomenon has been properly compensated with estimated parameters at the direct conversion RF repeater.

• Journal of the Korea Society of Computer and Information
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• v.5 no.4
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• pp.62-68
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• 2000

It was designed a high-speed analog input card that is a important device of ultrasonic testing flaw detector in the middle of non-destructive testing in this Paper. The A/D Board is inquired high-speed sampling rate and fast data acquisition system. This pater shows a design that has a function of Peak- Detection for ultrasonic testing by ISA Bus type and a 50MHz of A/D converter in order to do sampling more than quadruple frequency of transducer frequency.