• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• 한국지구물리탐사학회:학술대회논문집
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• 2005.05a
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• pp.187-194
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• 2005

A PC-based 8-channel seismic system has been developed and applied for bedrock mapping in near shore environment. The system is composed of an analog signal processor and an A/D converter installed on the computer, and a streamer with the group interval of 5 meters. The system is accomplished with a data acquisition program which controls the system and a data processing software. With the PC-based shallow marine seismic survey system high-resolution 2-D marine seismic profiles which have high S/N ratios can be obtained after appropriate data processing.

• Journal of Satellite, Information and Communications
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• v.9 no.2
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• pp.7-11
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• 2014

In this paper, we designed resistive MMIC mixer using $0.5{\mu}m$ p-HEMT process. This Mixer is designed to have a similar performance in -4 ~ 4 dBm local oscillator signal power level and to maintain a constant conversion loss and linear performance due to the variation of local signal. In order to have such characteristics, we designed new feedback circuit topology by using FET, and minimized performance change for LO signal power level variation, also obtain MMIC mixer characteristics which is able to apply in wideband. In the design result, When the LO signal power is -4 ~ 4 dBm, there was 6 dB conversion loss and it came up with the excellent result that IIP3 got over 30 dBm in 0.5 ~ 2.6GHz frequency band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.39-46
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• 2005

A DC-DC converter with digital controller is realized. the digital controller has several advantages such as robustness, fast design time, and high flexibility. however, since the DC-DC output voltage is analog, an analog-to-digital conversion scheme is always essential in all digital controllers. A simple and efficient delta-sigma modulator is used as a conversion scheme in out implementation. The measurement results show good voltage regulation

• Korean Journal of Optics and Photonics
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• v.16 no.1
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• pp.27-33
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• 2005

In this paper, a new wavelength converter using an SOA(Semiconductor Optical Amplifier)-loop-mirror for NRZ(NonReturn to Zero) optical data has been proposed and experimentally demonstrated. Conventional nonlinear fiber-loop-mirror methods can perform RZ-to-RZ, NRZ-to-RZ, and RZ-to-NRZ data format conversion, but NRZ-to-NRZ conversion has not been demonstrated until now. The experiment for the conversion from a 1300 nm NRZ data signal at 1.5 Gbps to a 1550 nm NRZ data one is successfully performed using a fiber-loop-mirror with 1300 nm-SOA.

• Proceedings of the Korea Society for Simulation Conference
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• 2000.04a
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• pp.180-185
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• 2000

발전소 등의 대규모 공정 플랜트에서 사용하고 있는 대부분의 상용 제어기는 PID 제어기이며, 온도 루프를 제외한 대부분의 제어루프가 PI 제어기를 채용하고 있다. 제어 시스템의 성능이 제어기 파라미터의 값에 의해 결정되므로, PI 제어기의 튜닝이 중요하다. 한편, 실제 현장에서의 PI 제어기의 튜닝은 많은 시간과 노력을 필요로 하는 시행착오에 의해서 이루어지고 있으며, 각 제어 루프 제어기 파라미터의 초기값 설정에 어려움을 갖고 있는 실정이다. PI 튜닝 기법이 많이 나와 있지만 시험 신호의 인가 문제로 인해 현장 활용에는 많은 어려움을 가지고 있다. 본 논문에서는 단순한 시험 신호로부터 PI 초기 설정값을 산출할 수 있는 방법에 대해서 알아본다. 또한 발전소에 적용된 국산 분산 제어 시스템을 보면, 대부분 데이터 로깅 시스템으로서만 활용되고 있고, 제어 시스템으로의 활용은 거의 이루어지지 않고 있으며, PID제어기에 대한 구현도 완벽하지 못하여 디지털 PI 제어기의구현 방법에 대한 고찰도 요구되고 있다. 본 논문에서는 디지탈 PI 제어기를 구현하는데 있어서 필요한 사항들, 즉 아날로그 제어기의 디지털 등가 제어기로의 변환 기법, 샘플링 주기의 결정 방법, 그리고 그 외에 공정 제어기가 가져야할 기능들에 대해서 언급한다. 그리고나서 PI 튜닝 기법과 아날로그 제어기의 디지털 등가 제어기로의 변환기법, 샘플링 주기 결정 방법 등에 대해 플랜트 모델을 선정하고 시뮬레이션을 통해 그 효용성을 보인다.

• The Journal of Information Technology
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• v.4 no.4
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• pp.51-63
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• 2001

Residue Number System has carry free operation and parallelism each modulus, So it is used for special purpose processor such as Digital Signal Processing and Neuron Processor. Magnitude comparison and sign detection are in need of Mixed Radix Conversion, and these operations are impediment to improve the operation speed. So in this Paper, MRC(Mixed Radix Converter) is designed using modified partitioned residue to speed up the operation of MRC, so it has progressed maximum twice operation time but increased the size of converter comparison to other converter.

• The Journal of the Acoustical Society of Korea
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• v.33 no.5
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• pp.300-308
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• 2014

Photoacoustic imaging is a useful tool for the diagnosis of atherosclerosis because it is capable of providing anatomical and pathological information at the same time. A photoacoustic signal detector is a pivotal element to achieve high spatial resolution, so that it should have broadband spectrum with a high center frequency. Since a photoacoustic imaging probe is directly inserted into blood vessel to diagnose atherosclerosis, the total size of the photoacoustic signal detector should be less than 1 mm. The main purpose of this paper is to demonstrate that PVDF can be used as an active material for the photoacoustic signal detector with a high frequency and broadband characteristic. The photoacoustic signal detector developed in this study was a single element ultrasound transducer with an aperture of $0.5{\times}0.5mm$ and the total size of 1 mm. In the design stage, the natural focal depth was adjusted for an effective focal area to cover the region of interest, i.e., 1~5 mm in depth. This was because geometrical focusing could not be used due to the small aperture. Through a pulse-echo test, it was ascertained that the developed photoacoustic signal detector has the -6 dB bandwidth ranging between 40.1 and 112.8 MHz and the center frequency of 76.83 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.129-134
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• 2014

This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.

• The Journal of the Korea Contents Association
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• v.11 no.4
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• pp.27-32
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• 2011

This paper presents a methodology for classifying sleep disturbance using electroencephalogram (EEG) signal at sleep stage 2 and principal component analysis. For extracting initial features, fast Fourier transforms(FFT) were carried out to remove some noise from EEG signal at sleep stage 2. In the second phase, we used principal component analysis to reduction from EEG signal that was removed some noise by FFT to 5 features. In the final phase, 5 features were used as inputs of NEWFM to get performance results. The proposed methodology shows that accuracy rate, specificity rate, and sensitivity were all 100%.