• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.237-243
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• 2012

In recent system-on-chip (SoC) designs, several hundred embedded memory cores have occupied the largest portion of the chip area. Therefore, the yield of SoCs is strongly dependent on the yield of the embedded memory cores. If all memories had built-in self repair (BISR) with optimal repair rates, the area overhead would be very large. A bit-map sharing method using a memory grouping is proposed to reduce the area overhead. Since the bit-map memory occupies the largest portion of the area of the built-in redundancy analysis (BIRA), the proposed bit-map sharing method can greatly reduce the area overhead of the BIRA. Based on the experimental results, the proposed method can reduce the area overhead by about 80%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.31-38
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• 2011

With the increasing demand for high-speed transmission systems, adaptive equalizers have been widely used in receivers to overcome the limited bandwidth of channels. In order to reduce the cost for testing high-speed receiver chips, on-chip eye-opening monitoring (EOM) technique which measures the eye-opening of data waveform inside the chip can be employed. In this paper, a 10-Gb/s adaptive 2-tap look-ahead decision feedback equalizer (DFE) with EOM function is proposed. The proposed EOM circuit can be applied to look-ahead DFEs while existing EOM techniques cannot. The magnitudes of the post-cursors are measured by monitoring the eye of received signal, and coefficients of DFE are calculated using them by proposed adaptation algorithm. The circuit designed in 90nm CMOS technology and the algorithm are verified with post-layout simulation. The DFE core occupies $110{\times}95{\mu}m^2$ and consumes 11mW in 1.2V supply voltage.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2000.05a
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• pp.118-121
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• 2000

본 논문에서는 FNNs(feedforwad neural networks)구현을 위한 새로운 학습 방안을 제안하였다. 제안된 방식은 온 칩 학습이 가능하도록 FNNs와 학습회로 사이에 스위칭 회로를 추가하여 단일패턴과 다중패턴 학습이 가능하도록 구현하였다. 학습 회로는 MEBP(modified error back-propagation) 학습 규칙을 적용하였고 간단한 비선형 시냅스 회로를 이용하여 구현하였다. 제안된 방식은 표준 CMOS 공정으로 구현되었고, MOSIS AMI $1.5\mu\textrm{m}$공정 HSPICE 파라메터를 이용하여 그 동작을 검증하였다. 제안된 학습방안 및 비선형 회로는 향후 학습 기능을 가진 대규모의 FNNs 구현에 매우 적합하리라 예상된다.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.226-232
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• 2005

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some 14% performance enhancement and 50% gate count reduction compared to the conventional ones.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1899-1907
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• 2013

This paper presents an efficient defect detection and classification system based on reference image for COF (Chip-on-Film) which encounters fatal defects after ultra fine pattern fabrication. These defects include typical ones such as open, mouse bite (near open), hard short and soft short. In order to detect these defects, conventionally it needs visual examination or electric circuits. However, these methods requires huge amount of time and money. In this paper, based on reference image, the proposed system detects fatal defect and efficiently classifies it to one of 4 types. The proposed system includes the preprocessing of the test image, the extraction of ROI, the analysis of local binary pattern and classification. Through simulations with lots of sample images, it is shown that the proposed system is very efficient in reducing huge amount of time and money for detecting the defects of ultra fine pattern COF.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.29-32
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• 2010

공정이 미세화 될수록 프로세서 상에서의 thermal management는 점점 중요해지고 있다. 칩의 온도가 임계 온도를 넘어 손상되거나, 시스템이 불능이 되는 상황을 방지하기 위해 그 동안 많은 기법들이 소개되어 왔다. 하지만 이러한 기법들은 시스템 전체를 끄거나 느려지게 함으로써 상당한 양의 성능 저하를 가져왔다. 이 논문에서는 프로세서의 가장 중요한 Hotspot인 Register File의 온도 관리를 위한 기법으로 Periodic Mapping을 제안하고, 이를 기존의 기법들과 비교해 본다.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.257-266
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• 2007

In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.