• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.3
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• pp.209-216
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• 2011

Recently the design of SoCs(System-on-Chips) in which TCM is embedded for high speed operation increases rapidly. In this paper, a parallel test structure for eDRAM-based TCM embedded in SoCs is proposed. In the presented technique, the MUT (Memory Under Test) is changed to parallel structure and it increases testability of MUT with boundary scan chains. The eDRAM is designed in structure for parallel test so that it can be tested for each modules. Dynamic test can be performed based on input-output data. The proposed techniques are verified their performance by circuits simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.766-767
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• 2013

본 논문에서는 차량 충돌 예방 레이더 시스템-온-칩용 24GHz 믹서(Mixer)를 제안한다. 이러한 회로는 24GHz의 동작주파수를 가지며, Gilbert 셀 구조로 구성된다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정 ($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 제안한 회로는 10.96dB의 변환이득으로 최근 발표된 연구결과 중 가장 우수한 수치를 보였다. 또한 7.62dBm의 우수한 IIP3의 특성과 -43.64dB의 입력/출력 반사손실 (S11/S22) 및 -49.3dB의 LO-RF간 격리 특성 (S12)으로 기존 연구결과 중 가장 우수한 결과를 각각 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.708-709
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• 2013

본 논문에서는 차량 충돌 예방 레이더 시스템-온-칩용 24GHz 믹서(Mixer)를 제안한다. 이러한 회로는 24GHz의 동작주파수를 가지며, Gilbert 셀 구조로 구성된다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정 ($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 제안한 회로는 10.96dB의 변환이득으로 최근 발표된 연구결과 중 가장 우수한 수치를 보였다. 또한 7.62dBm의 우수한 IIP3의 특성과 -43.64dB의 입력/출력 반사손실 (S11/S22) 및 -49.3dB의 LO-RF간 격리 특성 (S12)으로 기존 연구결과 중 가장 우수한 결과를 각각 보였다.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.56-61
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• 2000

Silicon semiconductor technology agrees that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduces verification time. This Paper describes the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.298-302
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• 2008

주어진 작은 크기의 칩 내부에 많은 기능 (예: 멀티미디어, 음성/영상 등)을 작동시키기 위해서는 고집적(high-integration)의 회로가 구현되게 된다. 이러한 고집적 회로는 작동할 때 상당한 양의 전력 소모를 유발하게 되어 결국 배더리 수명을 단축시키는 상황을 가지게 한다. 더욱 심각한 상황은 고 밀도의 칩 안에서의 많은 전력 소모는 열의 발생을 더욱 가속화 시키게 되며, 결국 칩 작동의 신뢰성(reliability)을 상당히 잃게 만든다. 본 연구에서는 칩의 작동에 따른 열 발생으로 유발되는 칩의 온도 상승을 감지하는 센서회로 구현에 관한 것이다. FPGA 칩은 주 목적의 기능을 수행하는 회로들을 구현함과 동시에 추가적으로 열 감지 센서 회로를 구현할 자원을 FPGA가 제공을 해 주어야 하는데, 주목적의 회로 공간(즉, 자원) 사용으로 인해 열 센서 회로 구현 자원이 충분하지 않을 경우나 여러 지역에 사용 가능한 자원이 소규모로 흩어진 경우 등 센서 구현을 위한 자원 탐색 및 구현 가능성에 대해 점검하는 알고리즘이 필요하다. 본 연구는 이러한 알고리즘을 개발하여 그 효용성을 실험을 통해 보이고 있다. 제안한 알고리즘의 특징은 Branch-and-Bound에 기반을 두고 있으며, 알고리즘의 수행 시간 단축을 위한 효과적인 search tree pruning 기법을 제안하고 있다.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.12
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• pp.540-551
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• 2008

Today's microprocessor designs are not free from temperature as well as power consumption. As processor technology scales down, an on-chip circuitry increases power density, which incurs excessive temperature (hotspot) problem. To tackle thermal problems cost-effectively, Dynamic Thermal Management (DTM) has been suggested: DTM techniques have benefits of thermal reliability and cooling cost. However, they require trade-off between thermal control and performance loss. This paper proposes a dual integer register file structure to minimize the performance degradation due to DTM invocations. In on-chip thermal control, the most important functional unit is an integer register file. It is the hotspot unit because of frequent read and write data accesses. The proposed dual integer register file migrates read data accesses by adding an extra register file, thus reduces per-unit dynamic power dissipation. As a result, the proposed structure completely eliminates localized hotspots in the integer register file, resulting in much less performance degradation by average 13.35% (maximum 18%) improvement compared to the conventional DTM architecture.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10a
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• pp.259-260
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• 2007

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.131-139
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• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.68-75
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• 2016

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.