• Electronics and Telecommunications Trends
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• v.14 no.3 s.57
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• pp.64-75
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• 1999

System-On-Chip 설계에서 이미 설계된 코어들을 연결시켜 시스템을 구성하기 위해 가장 필요한 기술 중에 하나는 온칩 버스 기술이라고 하겠다. 성능의 극대화를 위해 기존의 PCB상에서 사용되던 버스 대신에 별도의 온칩 버스들이 제안되고 있으며, 시스템 통합을 빠르고 용이하게 하기 위해서, 버스 자체에 대한 표준화나 전달물의 내용과 형식에 대한 표준화가 절실히 필요하며, VSIA에서 제안한 온칩 버스에 대한 표준 전달물과 그에 근거하여 온칩 버스를 비교한 결과를 제시한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.166-173
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• 2013

As the number of IPs and the communication volume among them have constantly increased, on-chip crossbar network is now the most widely-used on-chip communication backbone of contemporary SoCs. The on-chip crossbar network consists of multiple crossbars and the connections among the IPs and the crossbars. As the complexity of SoCs increases, it has also become more and more complex to determine the topology of the crossbar network. To tackle this problem, this paper proposes an on-chip crossbar network topology method for application-specific systems. The proposed method uses mixed integer linear programming to solve the topology synthesis problem, thus the global optimality is guaranteed. Unlike the previous MILP-based methods which represent the topology with adjacency matrixes of IPs and crossbar switches, the proposed method uses the communication edges among IPs as the basic element of the representation. The experimental results show that the proposed MILP formulation outperforms the previous one by improving the synthesis speed by 77.1 times on average, for 4 realistic benchmarks.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.212-214
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• 2012

데이터 집약적인 대부분의 애플리케이션들은 규칙적인 메모리 접근 패턴과 동시에 불규칙적인 접근 패턴을 커널 코드에 포함하고 있다. 그 동안 대부분의 메모리 접근 패턴 최적화 기법은 규칙적인 패턴에 집중되어 있었다. 하지만 암호화/통신 관련 애플리케이션에서는 불규칙한 패턴으로 메모리 접근의 대부분을 구성하는 경우가 많다. 이러한 불규칙한 메모리 접근 패턴을 대상으로 온칩메모리를 효율적으로 사용하도록 최적화 기법을 일반화하여 설계하는 일은 어려운 작업이기 때문에 관련 연구분야에 큰 진전이 없는 실정이다. 우리는 불규칙 메모리 접근 패턴 최적화 문제를 해결하기 위하여 데이터 클러스터링 기법을 제안하였다. 클러스터링은 접근되는 데이터의 시공간 지역성을 계산하여 이득이 큰 데이터들을 하나의 블록으로 구성하여 온칩메모리에 상주시키는 기본단위로 사용하는 기법이다. 본 기법을 이용하면 기존의 캐시메모리에 비하여 약 19% 에너지 소모를 절감할 수 있다.

• Journal of Korean Electronics
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• v.19 no.9
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• pp.37-43
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• 1999

• Proceedings of the Korea Information Processing Society Conference
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• 2020.11a
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• pp.92-95
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• 2020

나날이 커져가는 데이터 처리량의 수요를 충족시키기 위한 방법의 하나로 수십개의 코어와 여러 채널의 고대역폭 메모리를 탑재한 프로세서가 상위 슈퍼컴퓨터 시스템에 도입되어 사용되고 있다. 이러한 Scale-out 방식은 성능 한계를 크게 끌어올릴 수 있지만 제대로 된 작업 배분이 되지 않았을 때 성능이 떨어질 가능성이 있다. 본 연구에서는 인텔 KNL 프로세서의 고성능 온칩 메모리의 성능 벤치마크를 진행하여 병목 현상이 실제로 존재함을 확인하였다. 또한 이런 성능 저하 패턴을 찾아내고 원인을 분석하여 향후의 시스템에서 이러한 문제를 최소화하기 위해서 하드웨어, 시스템 소프트웨어 수준에의 보완 방안을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.568-573
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• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.345-348
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• 2013

This paper provides a method for compression and transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.465-474
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• 2005

For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.343-350
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• 2016

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.