• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.769-770
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• 2011

This paper presented a method constructing the ITSoC(Information Technology System-on-Chip). In order to implement the ITSoC, designers are increasing relying on reuse of intellectual property(IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. Also, embedded core in an ITSoC access mechanisms are required to test them at the system level. That is the goal, in theory. In practice, assembling an ITSoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discuss the main challenge in ITSoC designs using IP blocks and elaborates on the methodology and tools being put in place for addressing the problem. It explains ITSoC architecture and gives algorithmic details on the high-level tools being developed for ITSoC design.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.888-889
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• 2015

This paper presents a method of constructing the system-on-chip(SoC) based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-exiting components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

• Journal of Korean Electronics
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• v.19 no.2
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• pp.110-117
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• 1999

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.481-484
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• 2007

This paper presents a method of constructing the system-on-chip(SoC) based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-exiting components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

• Electronics and Telecommunications Trends
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• v.25 no.5
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• pp.84-96
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• 2010

국내 휴대폰 시장은 최근 급격한 변화의 시기를 맞고 있다. 음성정보 송 수신과 단순한 개인정보관리, 또는 멀티미디어 데이터 처리에 주력하던 피처폰 시장은 고사양의 운영체제, HD급 비디오, 수십만 가지의 앱(App.; Application), 고성능 디스플레이로 대표되는 스마트폰 시장으로 급격히 전환되고 있다. 이러한 스마트폰의 고사양화는 모바일프로세서, 베이스밴드 칩, 다양한 센서를 포함하는 스마트폰 하드웨어와 데스크톱 수준에 근접하는 고사양의 운영체제가 견인하고 있다. 특히, 모바일 프로세서는 스마트폰 기술 발전을 견인하는 핵심 부품으로서 다수의 프로세서와 외부인터페이스 장치를 포함하는 고성능, 저전력의 시스템온칩(SoC)이며 모바일프로세서의 동작속도, 전력소모량 등은 스마트폰의 성능을 가늠하는 척도로 인식되고 있다. 최근, 모바일프로세서는 스마트폰 시장을 넘어서 넷북, MID, 스마트 TV 등 다양한 산업영역에서 채용되고 있으며 2018년에 100억 개의 제품이 생산될 것으로 전망되어 모바일 시장의 폭발적인 성장을 견인하는 핵심 부품이다.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.369-370
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• 2007

본 논문에서는 IDLE 전송만을 수행하거나 버스접근빈도가 낮은 디폴트 마스터(Default Master)를 버스에 대한 접근빈도가 가장 높은 마스터로 재정의 하고, 버스접근빈도가 가장 높은 마스터를 찾기 위한 블록을 제작하여 추가하였다. 이 블록을 이용하여 버스에 대한 접근빈도와 데이터의 특성에 따라 디폴트 마스터를 재설정 해줄 수 있다 이로써 버스에 대한 접시간을 줄이고, 다중버스구조에서 단일버스구조와 동일한 전송이 가능하게 하여, 기존의 디폴트 마스터를 사용한 버스 구조에서 보다 효율적인 전송이 가능하다.

• The Journal of the Korea Contents Association
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• v.12 no.7
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• pp.11-20
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• 2012

This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.225-234
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• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.01a
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• pp.9-13
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• 2014

The performance of large scale software applications has been automatically increasing for last few decades under the influence of Moore's law - the number of transistors on a microprocessor roughly doubled every eighteen months. However, on-chip transistors limitations and heating issues led to the emergence of multicore processors. The energy efficient ARM based System-on-Chip (SoC) processors are being considered for future high performance computing systems. In this paper, we present a case study of two widely used parallel programming models i.e. MPI and MapReduce on distributed memory cluster of ARM SoC development boards. The case study application, Black-Scholes option pricing equation, was parallelized and evaluated in terms of power consumption and throughput. The results show that the Hadoop implementation has low instantaneous power consumption that of MPI, but MPI outperforms Hadoop implementation by a factor of 1.46 in terms of total power consumption to execution time ratio.