• Computational Structural Engineering
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• v.11 no.4
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• pp.135-146
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• 1998

대형 시스템의 건전성 평가를 위한 동적 재하시험에 있어서 변위를 측정하는 것보다 가속도를 측정하는 것이 수월하나 대부분의 공학적 기준은 응력과 비례관계를 지니는 변화를 기준으로 하고 있다. 본 연구에서는 시스템의 재하시험시 측정된 가속도신호를 이용하여 변위응답을 산정하는데 그 목적을 두고 적분을 위한 신호처리시 발생되는 문제점을 정상상태 및 천이영역에 대하여 규명하였다. 기존의 연구에서 고려하지 못하였던 초기조건의 항을 도입함으로써 시간영역의 적분과 주파수영역의 적분결과가 일치함을 해석적으로 입증하였으며 이동하중을 받는 보의 동적거동에 대하여 제시된 타당성을 검증하였다.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.12 no.2
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• pp.129-140
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• 1999

추계론적 해석은 구조계 내의 해석인수에 존재하는 공간적 또는 시간적 임의성이 구조계 반응에 미치는 영향에 대한 고찰을 목적으로 한다. 확률장은 구족계 내에서 특정한 확률분포를 가지는 것으로 가정된다. 구조계 반응에 대한 이들 확률장의 영향 평가를 위하여 통계학적 추계론적 해석과 비통계학적 추계론적 해석이 사용되고 있다. 본 연구에서는 비통계학적 추계론적 해석방법 중의 하나인 가중적분법을 제안하였다. 특히 구조계의 공간적 임의성이 큰 특성을 가지고 있는 반무한영역에 대한 적용 예를 제시하고자 한다. 반무한영역의 모델링에는 무한요소를 사용하였다. 제안된 방법에 의한 해석 결과는 통계학적 방법인 몬테카를로 방법에 의한 결과와 비교되었다. 제안된 가중적분법은 자기상관함수를 사용하여 확률장을 고려하므로 무한영역의 고려에 따른 해석의 모호성을 제거할 수 있다. 제안방법과 몬테카를로 방법에 의한 결과는 상호 잘 일치하였으며 공분산 및 표준편차는 무한요소의 적용에 의하여 매우 개선된 결과를 나타내었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.1068-1076
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• 1996

In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analyog current-mode active filters is proposed. Compared to the current-mode integrator which is proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter is designed with the proposed current-mode integrator. The designed circuits are fabricated using the ORBIT's $1.2{\mu}{\textrm{m}}$ deouble-poly double-metal CMOS n-well process. The experimental results show that the filter has -3dB cutoff frequency at 44.5MHz and 3mW power dissipation with single 3.3V power supply and also $0.12mm^{2}$ chip area.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.26-32
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• 2017

This paper presents a low power and high resolution incremental delta-sigma ADC that utilizes a passive integrator instead of an opamp-based active integrator. Opamp is a power-hungry block that involves tight design tradeoffs. To avoid the use of active integrator, the s-domain characteristic of an active integrator is first analyzed. Based on the analysis, an active integrator with low gain design is proposed as an alternative design method. To save power even more aggressively, a passive integrator with no static current is proposed. A 1st order single-bit incremental delta-sigma ADC using the proposed passive integrator is implemented in a 65nm CMOS process. Transistor-level simulation shows that the ADC consumes only 0.6uW under 1.2V supply while achieving SNDR of 71dB with 22kHz bandwidth. The estimated total power consumption including digital filter is 6.25uW, and resulting power efficiency is on a par with state-of-the-art A/D converters.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2009.04a
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• pp.304-307
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• 2009

본 논문에서는 3차원 모델링을 이용하여 원공을 갖는 알루미늄 판의 패치 보강효과에 대해 알아보고자 한다. 구조물의 노후화로 인해 높은 응력을 받는 부재의 응력 특이점에서 내구력이 급격하게 저하되거나 때로는 부재의 정적파괴를 유발시키는 원인을 제공한다. 이로 인해 과거에는 손상된 모재에 보강 재료를 연결시키기 위하여 리벳 또는 볼트와 같은 기계적 연결을 통해 보강하였으나 최근에는 접착패치보강 기법이 그 주류를 이루고 있다. 패치 보강시 일면 패치 보강으로 인하여 면외 휨 효과가 발생된다. 판의 두께 방향에 따른 응력집중계수를 별도로 분석하였다. 기존의 3차원 솔리드 요소는 해의 정확성은 뛰어난 반면에 상당한 컴퓨터 시간을 요구하는 단점을 가지고 있다. 이러한 문제를 극복하기 위해서, 본 논문에서는 각 층의 변위장을 2차원 형상함수와 1차원 형상함수의 조합으로 구성하여, 면내거동에 대한 p-세분화와 면외거동에 대한 p-세분화를 분리시키는 방식을 취한다. 또한, 에너지 함수의 적분시 Gauss-Lobatto 적분법을 사용하여 절점의 위치에서의 응력점을 구하는 경우, 외삽과정을 계산하는 단계를 생략하면서도, 해의 정확성 측면에서는 거의 차이가 없기 때문에 좀 더 효율적인 수치적분이 될 수 있다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.7
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• pp.38-45
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• 2002

This paper derives the electric field integral equation to calculate scattering from arbitrary large target above and radiating of an electric line source within a lossy ground. Sommerfeld’s type integral requires a lot of time to calculate and has some difficulties and limitations for an analysis region. But SDP (steepest descent path) integration gives fast calculation of the integral, and the result shows that SDP integration has the validity for all over the analysis region with fast evaluation. Moment method with SDP integration is used to calculate the scattering of an arbitrary large conducting target and the results are compared with that of the numerical integration with Gaussian quadrature rule and GPOF (generalized pencil of function) method.

• Journal of the Society of Naval Architects of Korea
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• v.29 no.1
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• pp.14-28
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• 1992

For a planar curve-sided paned with constant or linear density distributions of source or doublet in the singularity methods, Cantaloube and Rehbach(1986) show that the surface integral can be transformed into contour integral by using Stokes' formulas. As an extension of their formulations, this paper deals with a planar polygonal panel for which we derive the closed-forms of the potentials and the velocities induced by the singularity distributions. Test calculations show that the analytical evaluation of the closed-forms is superior to numerical integration(suggested by Cantaloube and Rehbach) of the contour integral. The compact and explicit expressions may produce accurate values of matrix elements of simultaneous linear equations in the singularity methods with much reduced computer tiome.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1477-1483
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• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.