• Title/Summary/Keyword: 스케줄링 TAM

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SA-Based Test Scheduling to Reduce the Test Time of NoC-Based SoCS (SA 기법 응용 NoC 기반 SoC 테스트 시간 감소 방법)

  • Ahn, Jin-Ho;Kim, Hong-Sik;Kim, Hyun-Jin;Park, Young-Ho;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.93-100
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    • 2008
  • In this paper, we address a novel simulated annealing(SA)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip(SoCs), on the assumption that the test platform proposed in [1] is installed. The proposed method efficiently mixed the rectangle packing method with SA and improved the scheduling results by locally changing the test access mechanism(TAM) widths for cores and the testing orders. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce the overall test time.

Shortest-Frame-First Scheduling Algorithm of Threads On Multithreaded Models (다중스레드 모델에서 최단 프레임 우선 스레드 스케줄링 알고리즘)

  • Sim, Woo-Ho;Yoo, Weon-Hee;Yang, Chang-Mo
    • Journal of KIISE:Software and Applications
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    • v.27 no.5
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    • pp.575-582
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    • 2000
  • Because FIFO thread scheduling used in the existing multithreaded models does not consider locality in programs, it may result in the decrease of the performance of execution, caused by the frequent context switching overhead and delay of execution of relatively short frames. Quantum unit scheduling enhances the performance a little, but it still has the problems such as the decrease in the processor utilization and the longer delay due to its heavy dependency on the priority of the quantum units. In this paper, we propose shortest-frame-first(SFF) thread scheduling algorithm. Our algorithm selects and schedules the frame that is expected to take the shortest execution time using thread size and synchronization information analyzed at compile-time. We can estimate the relative execution time of each frame at compile-time. Using SFF thread scheduling algorithm on the multithreaded models, we can expect the faster execution, better utilization of the processor, increased throughput and short waiting time compared to FIFO scheduling.

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NoC Test Scheduling Based on a Rectangle Packing Algorithm (Rectangle Packing 방식 기반 NoC 테스트 스케쥴링)

  • Ahn Jin-Ho;Kim Gunbae;Kang Sungho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.1 s.343
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    • pp.71-78
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    • 2006
  • An NoC (Networks-on-Chip) is an emerging design paradigm intended to cope with a future SoC containing numerous built-in cores. In an NoC, the test strategy is very significant for its practicality and feasibility. Among existing test issues, TAM architecture and test scheduling will particularly dominate the overall test performance. In this paper, we address an efficient NoC test scheduling algorithm based on a rectangle packing approach used for an SoC test. In order to adopt the rectangle packing solution as an NoC test scheduling algorithm we design the configuration about test resources and test methods suitable for an NoC structure. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the overall test time by up to $55\%$ in comparison with previous works.

A New Test Technique of SOC Test Based on Embedded Cores for Reducing SOC Test Time (SOC 테스트 시간 축소를 위한 새로운 내장 코어 기반 SOC 테스트 전략)

  • 강길영;김근배;임정빈;전성훈;강성호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.9
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    • pp.97-106
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    • 2004
  • A new test strategy for embedded SOC test is proposed. The SOC test is evaluated by the degree that is the amount of the total reduced test time. Since the test time for a embedded core is determined by the configuration of test wrapper, the total test time is decided by the length of the largest TAM used by the test wrapper. So the DFT(Design for Test) must be involved in the design flow. And the efficient test strategy must be settled. The all Previous test strategies are the methods that find a sub-optimal configurations of scan-chains to minimize the test time after the total TAM lines are divided into a few groups. But this is the NP-complete problem so that all attempts which examine such a TAM configuration and scan-chain division are impossible. In this thesis, a new methodology for this problem is proposed and the efficiency of the methodology is proved.

An Efficient Wrapper Design for SOC Testing (SOC 테스트를 위한 Wrapper 설계 기법)

  • Choi, Sun-Hwa;Kim, Moon-Joon;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.3
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    • pp.65-70
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    • 2004
  • The SOC(System on Chip) testing has required the core re-use methodology and the efficiency of test method because of increase of its cost. The goal of SOC testing is to minimize the testing time, area overhead, and power consumption during testing. Prior research has concentrated on only one aspect of the test core wrapper design problem at a test time. Our research is concentrated on optimization of test time and area overhead for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient wrapper design algorithm that improves on earlier approaches by also reducing the TAM(Test Access Mechanism) width required to achieve these lower testing times.