• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.252-257
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• 1998

본 논문은 입력 버퍼링 구조를 갖는 패킷 스위치에서 입력 확장 스위치 패브릭 구조를 통한 성능 개선에 관한 연구이다. 스위치 패브릭의 처리 능력 개선을 위한 다양한 구조에 대한 성능 및 설계 파라메터를 분석하고, 목적지별로 구분되는 입력 확장스위치 패브릭 구조를 제안하고 버스트 트래픽 환경에서 제안된 스위치의 성능을 분석한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.193-202
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• 2007

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches under Hot-spot environment is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch. The performance of the multiple-buffered $a{\times}a$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• Journal of KIISE:Information Networking
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• v.27 no.3
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• pp.331-338
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• 2000

온라인 화상회의, VOD 등의 멀티캐스트(multicast)특성을 갖는 서비스를 효율적으로 제공하기 위해서는 스위치 수준에서의 멀티캐스트 트래픽 처리를 위한 연구가 필요하다. ATM 스위치 증 입력 버퍼형은 하드웨어 구현 복잡도가 낮아 고속의 트래픽 처리와 대용량 스위치 구현에 적합한 반면, 높은 성능을 가지기 위해서는 임의접근(random access) 입력버퍼와 좋은 셀 스케쥴링 알고리즘이 필요하다. 본 논문에서는 입혁버퍼형 ATM 스위치에서의 멀티캐스트 셀 스케쥴링 알고리즘인 무충동 시간예약(CFTR)기법을 제안한다. CFTR 기법은 입력버퍼의 셀의 전송시점을 충돌이 없도록 예약함으로써 높은 처리율을 가질 수 있도록 하며, 이를 위해 입력단, 출력단 스케쥴러에 예약 테이블을 둔다. CFTR 기법은 각 출력 단 스케쥴러에서의 예약과정이 간단하고 독립적, 병렬적 수행이 가능하므로 고속 트래픽 처리에 적합하다. CFTR 기법의 성능평가를 위해 시뮬레이션을 통해 기존의 셀 스케쥴링 방식과 비교하며, 약간의 하드웨어 추가로 매우 좋은 성능을 보임을 알 수 있다.

• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.203-217
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• 2007

In this paper, a performance evaluation model of Networks with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the switch networks. The characteristic of a network with crossbar switches is determined by both the connection pattern of the switches and the limitation of data flow in a each switch. In this thesis, the evaluation models of three different networks : Multistage interconnection network, Fat-tree network, and other ordinary communication network are developed. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Two important parameters of the network performance, throughput and delay, are evaluated. The proposed model takes simple and primitive switch networks, i.e., no flow control and drop packet, to demonstrate analysis procedures clearly. It, however, can not only be applied to any other complicate modern switch networks that have intelligent flow control but also estimate the performance of any size networks with multiple-buffered switches. To validate the proposed analysis model, the simulation is carried out on the various sizes of networks that uses the multiple buffered crossbar switches. It is shown that both the analysis and the simulation results match closely. It is also observed that the increasing rate of Normalized Throughput is reduced and the Network Delay is getting bigger as the buffer size increased.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10c
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• pp.136-138
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• 2003

빠른 속도와 넓은 대역폭을 이용한 멀티미디어 데이터 전송이 가능하게 됨으로써 패킷 스위칭 네트워크로부터 발생되는 트래픽은 burstiness 성질을 보여준다. 이러한 트래픽은 전통적인 해석적 방법에서 네트워크의 성능평가를 위해 사용되고 있는 트래픽 모델과는 상당히 다른 self­similar 트래픽 성질을 갖고 있다는 것이 실제 트래픽을 측정한 결과 나타나고 있다. 일반적으로 ATM 스위치는 패킷을 효율적으로 전송하기 위해 다양한 공유 버퍼관리 방법을 적용한다. 따라서 본 논문에서는 공유 버퍼를 사용하여 다중 스위치로 상호 연결된 ATM 스위치에서 self­similar 트래픽이 이웃 스위치들 간에 미치는 영향을 통하여 초고속 네트워크의 성능을 분석한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1755-1764
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• 1997

In this paper, we proposed the mechanism for the buffer allocation and a cell scheduling method with logical separation a single buffer in the ATm switch, and analyzed the cell loss probability and the delay of each trafic (CBR/VBR/ABR) based on the weighted value and the dynamic cell service scheduling algorithm. The proposed switch buffering system classifies composite trafics incoming to the switch, according to the characteristic of traffic, then stores them in the logically separated buffers, and adopts the round-robin service with weighted value in order to transmit cells in buffers though one output port. We analyzed 4 cell service scheduling algorithms with dynamic round-robinfor each logically separated service line of a single buffer, in which buffers have the respective weighted values and 3 classes on mixed traffic which characteristized by traffic descriptor. In simulation, using SIMCRIPT II.5., we model the VBR and the ABR traffics as ON/OFF processes, and the CBR traffic as a Poisson processes. As the results of analysis according to the proposed buffer management mechanism and cell service algorithm, we have found that the required QoS of each VC can be quaranteed depends on a scale of weighted values allocated to buffers that changed the weighted values, and cell scheduling algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.113-122
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• 2001

Several guidelines can be developed for a satellite-based ATM switch. One of the most important of these is that the switch must provide a requirement for CLRs on the order of 10-10 to meet the QoS of high- performance traffic and avoid costly retransmissions. In this paper, the proposed approach shows not only the better traffic performance but also requires the little switching elements and buffers compared with original Knockout switch and other scheduling algorithm. As a result, the complexity becomes reduced. Simulation results indicate that proposed approach shows excellent cell loss ratio compared with existing switch architecture. Also, iii performance can be approached to the cell loss ratio, which is requirement for the satellite system, as window size increases. An(1 it shows thats low complexity is induced. Therefore, the proposed approach is appropriate for satellite on-board ATM switch architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1756-1764
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• 1996

In this paper, we propose a new switch element of buffered Banyan network and analysis it. The proposed switch element consists of CASO(Content ASsociated Output) buffers, its controller and 2*2 crossbar switch. This switch element increase the performance of buffered Banyan network by removing HOL blocking. Also, we analyze the proposed switch element by mathematical modelling method based on MY analysis model which is one of earier proposed models.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.394-397
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• 2003

In this paper, we describe the implementation of high performance buffer manager that is used in an advanced input-queued switch fabric. The designed buffer manager provides wire-speed cell/packet routing with low cost and tolerates the transmission pipeline latency of request and grant data. The buffer manager is implemented in a FPGA chip and supports the speed of OC-48c, 2.5Gbps per port.