• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.9-18
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• 1998

A single RF transceiver chip for an extended GSM handset application was designedm, fabricated and evaluated. A RFIC was fabricated by using silicon BiCMOS process, and then packaged in 80 pin TQFP of $10 {\times} 10 mm^{2}$ in size. As a result, it was achieved guite reasonable integraty and good RF performance at the operation voltage of 3.3V. This paper describes development results of RF receiver section of the RFIC, which includes LNA, down conversion mixer, AGC, switched capacitor filter and down sampling mixer. The test results show that RF receiver section is well operated within frequency range of 925 ~960 MHz, which is defined on the extended GSM specification (E-GSM). The receiver section also reveals moderate power consumption of 67 mA and minimum detectable signal of -105 dBm.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.1-9
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• 2010

This paper describes a ultrasonic signal processing front-end IC for distance range meter and body detector. The burst shaped ultrasonic signal is generated by a self oscillator and its frequency range is about 40[kHz]-300[kHz]. The generated ultrasonic signal transmit through piezo resonator. The another piezo device transduce from received ultrasonic signal to electrical signals. This front-end IC contained low noise amplifier, band pass filter, busrt detector and time pulse generator and so on. This IC has two type of new idea for improve function and performance, which are self frequency control (SFC) and Variable Gain Control amplifier (VGC) scheme. The dimensions and number of external parts are minimized in order to get a smaller hardware size. This device has been fabricated in a O.6[um] double poly, double metal 40[V] High Voltage CMOS process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.9
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• pp.2227-2235
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• 2009

This paper describes the system configuration and measured performances of a wireless power transmission system which utilizes microwave. The technically final target of this system is to provide DC power to various mobile terminals within limited spaces such as buildings, conference rooms, and so on. The prototype system is built using in-house designed and fabricated circuits such as microwave oscillator, high power amplifier, microstrip patch antenna, low pass filter, and detector/rectifier. The fixed RF power of 29.3dBm at 2.4GHz is produced from the high power amplifier and transmitted through the transmitting antenna, while the received RF power at the receiving antenna is transformed into DC power through the detector/rectifier. The measured change of DC voltage according to the distance between transmitting and receiving antenna is described.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.49-55
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• 2013

A high-voltage highly-integrated analog front-end (AFE) IC for medical ultrasound imaging applications is implemented using standard 0.18-${\mu}m$ CMOS process. The proposed AFE IC is composed of a high-voltage (HV) pulser utilizing stacked transistors generating up to 15 Vp-p pulses at 2.6 MHz, a low-voltage low-noise transimpedance preamplifier, and a HV switch for isolation between the transmit and receive parts. The designed IC consumes less than $0.15mm^2$ of core area, making it feasible to be applied for multi-array medical ultrasound imaging systems, including portable handheld applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1534-1540
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• 2005

The direct conversion method is classified into the structure using the mixing technology and six-port scheme. In the view point of complexity and integration the direct conversion method using the six-port scheme is superior to that with mixing technology. Expecially, the six-port direct conversion technology provides the low power consumption and the broad-band characteristic. In this paper, the six-port direct conversion receiver with the branch-line coupler and the ring hybrid coupler is desisted respectively. The performances of the designed six-port schemes are analyzed and the six-port scheme with superior performance characteristics is proposed.

• Journal of IKEEE
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• v.15 no.3
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• pp.205-210
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• 2011

A novel hysteresis tunable monolithic comparator circuit based on a 0.35 ${\mu}m$ CMOS process is suggested in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V. The threshold voltage of the suggested comparator circuit is controlled by 234mV by change of 4 digital control bits in the simulation, which is a close agreement to the analytic calculation.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.38-42
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• 2005

CMOS analog lowpass filters using speech signal bandwidth for a Asymmetrical Digital Subscriver Line(ADSL) modem are presented. Designed active lowpass filters are composed of the CMOS complementary high-swing cascode stage which can increase transconductance of an active element. As a result, their cutoff frequency are 138kHz and 1,100kHz respectively. A low-voltage high-swing cascode integrator which improved on a gain and unit gain frequency used to design the filters. The designed filters are verified by HSPICE simulation with the $0.251{\mu}m\;CMOS\;n-well$ Parameter and a single 2.5V power supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.481-484
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• 2005

The direct conversion method is classified into the structure using the mixing technology and six-port scheme. In the view point of complexity and integration the direct conversion method using the six-port scheme is superior to that with mixing technology. Expecially, the six-port direct conversion technology provides the low power consumption and the broad-band characteristic. In this paper, the six-port direct conversion receiver with the branch-line coupler and the ring hybrid coupler is designed respectively. The performances of the designed six-port schemes are analyzed and the six-port scheme with superior performance characteristics is proposed.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.82-90
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• 2014

In this paper, a couple of 4-channel differential transimpedance amplifier arrays are realized in a standard 0.18um CMOS technology for the applications of linear LADAR(laser detection and ranging) systems. Each array targets 1.25-Gb/s operations, where the current-mode chip consists of current-mirror input stage, a single-to-differential amplifier, and an output buffer. The input stage exploits the local feedback current-mirror configuration for low input resistance and low noise characteristics. Measurements demonstrate that each channel achieves $69-dB{\Omega}$ transimpedance gain, 2.2-GHz bandwidth, 21.5-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -20.5-dBm), and the 4-channel total power dissipation of 147.6-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations. Meanwhile, the voltage-mode chip consists of inverter input stage for low noise characteristics, a single-to-differential amplifier, and an output buffer. Test chips reveal that each channel achieves $73-dB{\Omega}$ transimpedance gain, 1.1-GHz bandwidth, 13.2-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -22.8-dBm), and the 4-channel total power dissipation of 138.4-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.