• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.6
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• pp.1181-1188
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• 2017

The unit and fundamental units of number fields are important to number field sieves testing primality of more than 400 digits integers and number field seive factoring the number in RSA cryptosystem, and multiplication of ideals and counting class number of the number field in imaginary quadratic cryptosystem. To minimize the time and space in H/W implementation of cryptosystems using fundamental units, in this paper, we introduce the Dirichlet's unit Theorem and propose our process of generating the fundamental units of the number field. And then we present the algorithm generating our fundamental units of the number field to minimize the time and space in H/W implementation and implementation results using the algorithm over the number field.

• Journal of the Korean Institute of Intelligent Systems
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• v.7 no.5
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• pp.34-45
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• 1997

In this paper, we present hardware implemcntation of self-organizing feature map (SOFM) neural networkwith constant adaptation gain and binary reinforcement function on FPGA. Whereas a tnme-varyingadaptation gain is used in the conventional SOFM, the proposed SOFM has a time-invariant adaptationgain and adds a binary reinforcement function in order to compensate for the lowered abilityof SOFM due to the constant adaptation gain. Since the proposed algorithm has no multiplication operation.it is much easier to implement than the original SOFM. Since a unit neuron is composed of 1adde $r_tracter and 2 adders, its structure is simple, and thus the number of neurons fabricated onFPGA is expected to he large. In addition, a few control signal: ;:rp sufficient for controlling !he neurons.Experimental results show that each componeni ot thi inipiemented neural network operates correctlyand the whole system also works well.stem also works well.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.1-7
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• 1999

We present VLSI architecture for a high performance 2-D DCT processor which is used compressing system of real time image processing or HDTV using fast computational algorithm of the Optimized Integer Cosine Transform(OICT). The coefficients of the OICT are integer, so the OICT performs only the integer operations for both forward and inverse transform. Therefore the proposed architecture could be greatly enhanced in improving the speed, reduced the hardware cost considerably by replacing the multiplication operations with shift and addition operations compared with DCT which performs floating-point operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.33-39
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• 2006

In this paper we propose the Modified Karatsuba-Ofman algorithm for polynomial multiplication to polynomials of arbitrary degree. Leone proposed optimal stop condition for iteration of Karatsuba-Ofman algorithm(KO). In this paper, we propose a Non-Redundant Karatsuba-Ofman algorithm (NRKOA) with removing redundancy operations, and design a parallel hardware architecture based on the proposed algorithm. Comparing with existing related Karatsuba architectures with the same time complexity, the proposed architecture reduces the area complexity. Furthermore, the space complexity of the proposed multiplier is reduced by 43% in the best case.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.6
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• pp.105-113
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• 2001

Recently, Gallant, Lambert arid Vanstone introduced a method for speeding up the scalar multiplication on a family of elliptic curves over prime fields that have efficiently-computable endomorphisms. It really depends on decomposing an integral scalar in terms of an integer eigenvalue of the characteristic polynomial of such an endomorphism. In this paper, by using an element in the endomorphism ring of such an elliptic curve, we present an alternate method for decomposing a scalar. The proposed algorithm is more efficient than that of Gallant\`s and an upper bound on the lengths of the components is explicitly given.

• 한국공간정보시스템학회:학술대회논문집
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• 2007.06a
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• pp.111-116
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• 2007

현재 한강수계를 제외한 3대강 수계에서 수질오염총량관리제도가 의무제로써 시행되고 있다. 그러나 과학적 타당성과 외국의 성공사례들로 하여금 한강수계에 대해서도 수질오염총량제도를 의무제화 하려는 시도가 추진되고 있고 있는 실정이다. 이 제도가 한강수계에도 도입된다면, 한강권역에 포함되는 모든 지자체는 해당 유역에서 하천으로 유입되는 배출부하량을 할당받은 할당부하량 이하로 관리하여야만 정해진 유역의 목표수질을 달성할 수 있으며, 배출부하량 관리를 계획한데로 이행하지 못한 지자체는 범칙금 내지는 행정제재를 받게 된다. 따라서 체계적이고 과학적인 모니터링 및 분석 수단이 필요하다. 이 연구는 환경부 고시 한강기술지침에 의거하여 GIS를 이용하여 인천일대의 오폐수 발생부하량 및 배출부하량을 제시하고 과학적인 오염물질 삭감방안을 모색하는 것을 목적으로 진행되었다. 생활계, 산업계, 축산계, 양식계의 4 가지로 분류된 점오염원과 토지 이용 분류에 따른 비점오염원에 대한 각각의 발생부하량을 GIS를 통해 산정하고, 모든 오염원별로 처리경로를 고려하고 처리시설별, 방법별 삭감 효율을 반영하여 배출부하량을 산정하여 GIS상에서 제시하고 분석하였다. 인천일대는 인근지역에 비해 인구밀도가 높고 산업단지가 발달하여 생활계와 산업계 오염원에 의한 발생부하량 및 배출부하량이 많았으며, 특정 오염물에 대해서는 삭감 계획이 필요함을 확인할 수 있었다. 따라서 수질오염총량관리제도에 대비하고 실제 수질 개선을 위하여 본 연구의 결과를 바탕으로 수질관리를 위한 시스템의 보완 및 삭감계획의 수립에 관한 연구가 필요하다.알 수 있었다. 이상의 결과를 토대로 기존 압출추출방법과 초임계 추출 방법을 비교한 결과 $\gamma$-토코페롤의 농도가 1.3${\~}$1.6배 증가함을 확인할 수 있었다.게 상관성이 있어 앞으로 심도 있는 연구가 더욱 필요하다.qrt{F}}}{\pm}e_0$)에서 단정도실수 및 배정도실수의 역수 제곱근 계산에 필요한 평균 곱셈 횟수를 계산한다 이들 평균 곱셈 횟수를 종래 알고리즘과 비교하여 본 논문에서 제안한 알고리즘의 우수성을 증명한다. 본 논문에서 제안한 알고리즘은 오차가 일정한 값보다 작아질 때까지만 반복하므로 역수 제곱근 계산기의 성능을 높일 수 있다. 또한 최적의 근사 역수 제곱근 테이블을 구성할 수 있다. 본 논문의 연구 결과는 디지털 신호처리, 컴퓨터 그라픽스, 멀티미디어, 과학 기술 연산 등 부동소수점 계산기가 사용되는 분야에서 폭 넓게 사용될 수 있다.>16$\%$>0$\%$ 순으로 좋게 평가되었다. 결론적으로 감농축액의 첨가는 당과 탄닌성분을 함유함으로써 인절미의 노화를 지연시키고 저장성을 높이는데 효과가 있는 것으로 생각된다. 또한 인절미를 제조할 때 찹쌀가루에 8$\%$의 감농축액을 첨가하는 것이 감인절미의 색, 향, 단맛, 씹힘성이 적당하고 쓴맛과 떫은맛은 약하게 느끼면서 촉촉한 정도와 부드러운 정도는 강하게 느낄수 있어서 전반적인 기호도에서 가장 적절한 방법으로 사료된다.비위생 점수가 유의적으로 높은 점수를 나타내었다. 조리종사자의 위생지식 점수와 위생관리

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.59-68
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• 2002

In this paper, we design the two-dimensional Discrete Wavelet Transform (2D DWT) filter that is widely used in various applications such as image compression because it has no blocking effects and relatively high compression rate. The filter that we used here is two-channel four-taps QMF(Quadrature Mirror Filter) Lattice filter with PR (Perfect Reconstruction) property. The proposed DWT architecture, with two consecutive inputs shows an efficient performance with a minimum of such hardware resources as multipliers, adders, and registers due to a simple scheduling. The proposed architecture was verified by the RTL simulation, and utilizes the hardware 100%. Our architecture shows a relatively high performance with a minimum hardware when compared with other approaches. An efficient memory mapping and address generation techniques are introduced and the fixed-point arithmetic analysis for minimizing the PSNR degradation due to quantization is discussed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.352-358
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• 2004

This paper is studied the improvement of performance for moving picture encoder using H.263. This is used the new motion vector search algorithm using a relation with neighborhood search point and is applied the integer DCT for the encoder. The integer DCT behaves DCT by the addition operation of the integer using WHT and a integer lifting than conventional DCT that needs the multiplication operation of a floating point number. Therefore, the integer Dn can reduce the operation amount than basis DCT with having an equal PSNR. The new motion vector search algorithm is showed almost similar PSNR as reducing the operation amount than the conventional motion vector search algorithm. To experiment a compatibility of the integer DCT and the conventional DCT, according to result compare case that uses a method only and case that uses the alternate two methods of the integer DCT or the conventional DCT to H.263 encoder and decoder, case that uses the alternate two methods is showed doing not deteriorate PSNR-and being each other compatible visually than case that uses an equal method only.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.9
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• pp.1158-1165
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• 2021

This paper proposes a CNN accelerator which is optimized Pooling layer operation incorporated in Multiplication And Accumulation(MAC) to reduce the memory size. For optimizing memory and data path circuit, the quantized 8bit integer weights are used instead of 32bit floating-point weights for pre-training of MNIST data set. To reduce chip area, the proposed CNN model is reduced by a convolutional layer, a 4*4 Max Pooling, and two fully connected layers. And all the operations use specific MAC with approximation adders and multipliers. 94% of internal memory size reduction is achieved by simultaneously performing the convolution and the pooling operation in the proposed architecture. The proposed accelerator chip is designed by using TSMC65nmGP CMOS process. That has about half size of our previous paper, 0.8*0.9 = 0.72mm². The presented CNN accelerator chip achieves 94% accuracy and 77us inference time per an MNIST image.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.