• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2861-2873
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• 1997

An FPU(Floating Point unit) is the principle component in high performance computer and is placed on a chip together with main processing unit recently. As a Processing speed of the FPU is accelerated, the rounding stage, which occupies one of the floating point Processing steps for floating point operations, has a considerable effect on overall floating point operations. In this paper, by studying and analyzing the processing flows of the conventional floating point adder/subtractor, multipler and divider, which are main component of the FPU, efficient rounding mechanisms are presented. Proposed mechanisms do not require any additional execution time and any high speed adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.55-64
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• 2005

In this paper, we designed floating point units to accelate real-time 3D Graphics for Geometry processing. Designed floating point units support IEEE-754 single precision format and we confirmed 100 MHz performance of floating point add/mul unit, 120 MHz performance of floating point NR inverse division unit, 200 MHz performance of floating point power unit, 120 MHz performance of floating point inverse square root unit at Xilinx-vertex2. Also, using floating point units, designed Geometry processor and confirmed 3D Graphics data processing.

• Proceedings of the Korean Environmental Sciences Society Conference
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• 2001.11a
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• pp.126-127
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• 2001

폐산으로부터 얻은 magnetite와 시약으로 부터 얻은 magnetite는 거의 비슷한 특성을 보여주고 있으며, co-polymer성 계면활성제인 polyoxyethylene nonylphenyl ether (POENPE)는 친수기(polyoxyethylene)와 소수기(nonylphenyl ether )기를 동시에 갖고 있으므로 수분이 함유된 소수성 magmetite에 친수기가 접근하여 기름에 유화시킴으로서 자성유체의 분산율을 상승시키지만 과잉으로 첨가하면 오히려 분산율이 저하된다. 이 현상은 미셀을 형성하여 오히려 소수성이 친수성으로 변화함으로서 자성유체의 분산율을 저하시키고 기름의 제거 효율을 저하시키는 것으로 사료된다.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10a
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• pp.135-138
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• 2006

본 논문에서는 텍스처 매핑을 처리하기 위한 텍스처 유닛 하드웨어 설계에 효율적인 새로운 유동형 소수점 포맷을 제안한다. 기존 고정 소수점 포맷은 하드웨어가 간단한 반면 고품질 텍스처 처리를 수행할 경우 오버플로우/언더플로우가 발생하며 부동 소수점 포맷은 이를 해결할 수 있으나 하드웨어가 복잡하다. 제안한 방식은 오버플로우/언더플로우를 해결하면서 부동소수점보다 하드웨어 크기를 줄여서 본 포맷을 적용한 가산기는 부동소수점보다 26% 작으며 곱셈기는 고정/부동 소수점보다 절반 이상으로 작다. 따라서 제안한 포맷은 100Mhz 이상의 빠른 동작이 가능하며 모바일 3차원 그래픽 가속기의 텍스처 유닛 설계에 효과적이다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.611-614
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• 2005

1970년대 말까지 초창기에 출시된 컴퓨터들은 부동 소수점을 표현하기 위한 자신들의 내부적 표현방식을 사용하였다. 따라서 각 컴퓨터마다 부동 소수점 연산에 대한 계산 결과가 약간씩 차이가 나기도 하였다. 이러한 문제점을 해결하기 위해 IEEE에서는 부동 소수점에 대한 표준안을 제안하였다. 이는 서로 다른 컴퓨터 간에 부동 소수점 데이터의 교환이 가능하게 할 뿐만 아니라 하드웨어 설계자들에게도 정확한 모델을 제공하는 것이 목적이었다. 이 당시 제정된 부동 소수점 표준안은 IEEE Standard 754 부동 소수점이며, 오늘날 인텔 CPU 기반의 PC, 매킨토시 및 대부분의 유닉스 플랫폼에서 컴퓨터 상의 실수를 표현하기 위해 사용하는 가장 일반적인 표현 방식으로 발전하였다. 본 논문에서는 부동 소수점의 기본적인 표현방식에 대해 연구하고, 이 중 32 bit 단일 정밀도 부동 소수점 가산기를 Microsoft Visual C++ 6.0을 이용해 시뮬레이션하고 이를 VHDL로 구현한다.

• Journal of the Korean Applied Science and Technology
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• v.37 no.2
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• pp.250-259
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• 2020

The solubilization constant (K_s) was determined by the UV-Vis method to investigate the interaction between organic matter (solubilized substance) and surfactant in solubilization. Solubilization constants and thermodynamic functions, according to the hydrophobic interaction between organic mater (4-alkylanilines with different alkyl substituent length) and cationic surfactants (DTAB, TTAB, and CTAB, having different hydrophobic lengths), were measured and calculated at various temperatures and compared with each other. As a result, the hydrophobic interactions between organic matters and cationic micelles increased with increasing the chain length of solute's substituent as well as surfactant's hydrophobe. However, the hydrophobic effect by the alkyl substituent of organic matter was greater than the hydrophobic effect by the surfactant. In addition, the results of the calculated thermodynamic functions showed that 4-alkylaniline was solubilized at the deep place in the micelle and its solubilization was greatly dependent on both the hydrophobic effects of organic matter and surfactant. At the calculated iso-structural temperature, the difference between the maximum and minimum values was less than 1K within the experimental conditions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.547-554
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• 2008

In this paper, two-stage pipelined floating-point multiplier (FP-MUL) is designed. The FP-MUL processor supports single precision multiplication for 3D graphic APIs, such as OpenGL and Direct3D and has area-efficient and low-latency architecture via saturated arithmetic, area-efficient sticky-bit generator, and flagged prefix adder. The FP-MUL has about 4-ns delay time under $0.13{\mu}m$ CMOS standard cell library and consists of about 7,500 gates. Because its maximum performance is about 250 MFLOPS, it can be applicable to mobile 3D graphics application.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.409-416
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• 2024

With the expansion of floating-point operation requirements for fast high-speed data signal processing and logic operations, the speed of the floating-point operation unit is the key to affect system operation. This paper studies the performance characteristics of different floating-point multiplier schemes, completes partial product compression in the form of carry and sum, and then uses a carry look-ahead adder to obtain the result. Intel Quartus II CAD tool is used for describing Verilog HDL and evaluating performance results of the floating point multipliers. Floating point multipliers are analyzed and compared based on area, speed, and power consumption. The FMAX of modified Booth encoding with Wallace tree is 33.96 Mhz, which is 2.04 times faster than the booth encoding, 1.62 times faster than the modified booth encoding, 1.04 times faster than the booth encoding with wallace tree. Furthermore, compared to modified booth encoding, the area of modified booth encoding with wallace tree is reduced by 24.88%, and power consumption of that is reduced by 2.5%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.72-81
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• 2011

In this paper, we proposed and designed a novel floating point converter which supports single and double precisions of IEEE754 standard. The proposed convertor supports conversions between floating point number single/double precision and signed fixed point number(32bits/64bits) as well as conversions between signed integer(32bits/64bits) and floating point number single/double precision and conversions between floating point number single and double precisions. We defined a new internal format to convert various input types into one type so that overflow checking could be conducted easily according to range of output types. The internal format is similar to the extended format of floating point double precision defined in IEEE754 2008 standard. This standard specifies that minimum exponent bit-width of the extended format of floating point double precision is 15bits, but 11bits are enough to implement the proposed converting unit. Also, we optimized rounding stage of the convertor unit so that we could make it possible to operate rounding and represent correct negative numbers using an incrementer instead an adder. We designed single cycle data path and 5 cycles data path. After describing the HDL model for two data paths of the convertor, we synthesized them with TSMC 180nm technology library using Synopsys design compiler. Cell area of synthesis result occupies 12,886 gates(2 input NAND gate), and maximum operating frequency is 411MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.1
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• pp.95-103
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• 2009

We improve the performance of WCDMA repeater by cancelling the feedback interference radio signal under the fixed point implementation. Floating-point DSP or FPGA to implement the ICS algorithm may have an disadvantage of high cost, To solve this problem, we suggest the ICS algorithm based on LMS under fixed point operation, and show the validity of our results by comparing with the floating-point results through numerical simulation.