• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.109-118
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• 2007

As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.3
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• pp.40-47
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• 1997

안테나의 특성은 셀룰러 시스템의 서비스 품질에 직접적으로 영향을 미치는 요소가 되며, 특히 섹터화로 인한 용량의 증가를 기할 수 있는 CDMA 시스템의 경우에는 매우 중요한 의미를 갖는다. 본 논문의 지향성 안테나를 이용하여 전력 제어된 CDMA 셀을 섹터화할 경우 얻을 수 있는 용량의 이득을 논의한다. 용량의 측면에서 이상적인 안테나 패턴과 비교할 때 실제 안테나 패턴의 역방향 링크 용량 효율을 해석적으로 구한다. 셀룰러 CDMA 시스템의 용량은 동일한 주파수 대역을 사용할 수 있는 최대 통신 채널의 수이므로 용량 효율은 결국 주파수 스펙트럼 이용 효율을 의미한다. 측정된 반사판 섹터 안테나 패턴을 대상으로 분석한 결과를 제시하고 패턴 특성과 섹터 셀의 배치 구조에 따라 용량 효율이 86~97%로 변화함을 보인다.

• Journal of the Korean Institute of Intelligent Systems
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• v.9 no.6
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• pp.634-643
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• 1999

This paper concerns an implementation of f~rry logic controller (FLC') on a reconfigurahle FP

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.1
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• pp.69-74
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• 2021

This paper introduces a low-power voltage-controlled oscillator(VCO) with filters that consist of resistors and capacitors. The proposed VCO contains a 5-stage current mode buffer, and each buffer cell has a resistor-capacitor filter that connects input and output terminals. The filter adds a zero to the buffer cell. Because the zero moves the oscillation condition to high frequencies, the proposed VCO can generate a high frequency clock with low power consumption. The proposed circuit has been designed with 0.18 ㎛ CMOS process. The power consumption is 9.83 mW at 2.7 GHz. The proposed VCO shows 3.64 pJ/Hz in our simulation study, whereas the conventional circuit shows 4.79 pJ/Hz, indicating that our VCO achieves 24% reduction in power consumption.

• Proceedings of the KIPE Conference
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• 2009.11a
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• pp.246-248
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• 2009

본 논문에서는 장력 검출 장치(로드셀, 댄서 등) 가장착되어 있는 생산 설비에서 강선, 강판, 제지, 섬유, 비닐 등과 같은 소재의 장력을 정밀하게 제어하기 위한 인버터의 장력 제어 전용 PID 제어기와 직경 또는 소재의 두께를 실시간으로 추정하여 인버터의 출력 주파수를 보정하는 추정기를 제안한다. 본 논문에서 제안된 방법을 다양한 용량(0.37kW~160kW) 대의 인버터에 탑재하여 실제 부하에 적용함으로써 산업 현장에서 요구하는 수준이상의 우수한 제어 성능을 나타냄을 확인하였다.

• Journal of the Korea Convergence Society
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• v.8 no.11
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• pp.49-56
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• 2017

Curling sweeping is one of important motion to control the position of the curling stone, and sweeping speed and applied force to the broom pad are major research subjects. In this study, a device was developed to measure the force applied to the curling broom pad in curling sweeping motion, and two load cells were mounted between the broom pad and pad holder. Analog signals generated from the load cells were sampled about 300 times per second using a micro controller, and then converted to 10-bit digital signals. Calibration of the load cell and set up of regression equations to convert the measured electrical signals into mass (force) was done by three M1 class weights, and the developed system was designed as wearable device to minimize increasing of total weight of the broom. Same force was applied to the developed system and a force plate that was using as a reference force measurement system in field of sports, and the difference between the measured values were showed about $0.909{\pm}1.375N$(mean and standard deviation). The developed system could be applied other kinds of study which required force measurement function similar to sweeping motion.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.57-65
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• 1999

This paper deals with stand-alone photovoltaic system(SPVS) with charge and discharge controller. Main power source of SPVS are generally solar cell and battery. Therefore SPVS can be classified into variable types in accordance with connection type between battery and solar cell. Mainly used one of them is direct connection type which has advantages such as simple structure and simple controller. However most big drawback of this system is energy loss by voltage disharmony between solar cell and battery. Therefore SPVS with charge and discharge controller which can operate solar cell at maximum power point is suggested and designed with instantaneous controller. And system operating characteristics are verifieded by experiment with a laboratory prototype in this paper.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1164-1170
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• 2002

In the ACE2000 MPLS system, MPLS Interface Module(MIM) is composed of an ATM Interface Module and a HFMA performing a packet forwarding. In the MIM, the HFMA RSAR receive cells from the Physical layer and reassemble the cells. And the IP Lookup controller perform a packet forwarding after packet classification. Forwarded packet is segmented into cells in the HFMA TSAR and transfer to the ALMA for the transmission to an ATM cell switch. When the MIM make use of an ATM Interface Module, it directly connect the ALMA with a PHY layer using the UTOPIA Level2 interface. Then, an ALMA performs Master Mode. Also, the HFMA TSAR performs the Master Mode in the MIM. Therefore, the UTOPIA-L2 Controller of the Slave Mode require for interfacing between an ALMA and a HFHA TSAR. In this paper, we implement the architecture and cell control mechanism for the UTOPIA-L2 Controller supporting Multi-ports.

• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.399-405
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• 2009

This paper proposes a design of attenuator based on meta-material structure and its application. The unit-cell attenuator based on the lossy transmission line consists of the CRLH(Composite Right/Left Handed) transmission line and PIN diodes to be controlled internal loss according to diode bias voltage to change resistance of diode. Also, to reduce the initial losses, there is used parallel connection of PIN diodes. To increase attenuations, it is connected a cascade unit-cell of attenuator with periodic structure. The attenuation quantities of unit-cell are about 10dB and phase variations are 15o maximum at 1.5 GHz ~ 2.5 GHz. Also, its application is represented a vector modulator.