• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.123.2-123.2
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• 2011

$ALU^+$ 태양전지는 PN접합을 후면에서 즉, Al을 소성하여 형성시키기 때문에 얼마나 균일하고 두껍게 형성하는 것이 가장 중요하다. 소성(Firing)은 태양전지 제조 과정에서 후면의 접촉을 위한 중요한 공정이다. 본 연구에서는 상업화가 가능한 n-type $ALU^+$ Emitter 태양전지에서 소성 횟수에 따른 특성을 연구 하였다. $ALU^+$ emitter 형성의 최적화를 위해 소성온도를 가변하고, 최적화된 온도에서 소성 횟수에 따른 DIV 측정을 통해 셀을 분석 하였다. 소성 횟수는 1~3회로 하였고, 그 결과 단락전류 밀도(Jsc)가 33.57mA/$cm^2$로 처음보다 15.1%증가 하였고, 곡선인자(Fill Factor)는 3회에서 66.04%로 218%증가 하였다. Al을 짧은 시간 안에 소성을 시키므로 해서 후면의 $P^+$ Emitter가 균일하게 형성되었기 때문에 개방전압(Voc)의 증가를 확인하였다. 본 연구를 통해 $ALU^+$ 태양전지의 후면 Aluminium 소성 조건의 최적화를 통하여 $ALU^+$ emitter가 충분히 형성되지 못하면 누설전류가 발생되고 직렬저항(Rs)이 크게 증가하여 개방전압(Voc) 및 단락전류밀도(Jsc)의 감소가 발생하게 되고, 직렬저항(Rs)의 증가와 병렬저항(Rsh)의 감소는 Fill Factor의 급격한 감소를 초래하게 됨을 알 수 있다. 이를 개선하면 태양전지 효율을 상승시키는 결과를 얻을 수 있음을 확인하였다.

• Journal of the Korean Vacuum Society
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• v.19 no.5
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• pp.391-396
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• 2010

The pn junction for solar cell was prepared on p-type Si wafer by the furnace using the $POCl_3$ and oxygen mixed precursor to research the characteristic of interface at pn junction. The sheet resistance was decreased in accordance with the increasing the diffusion process time for n-type doping on p-type Si wafer. The electron affinity at the interface in the pn junction was decreased with increasing the amount of n-type doping and the sheet resistance also decreased. Consequently, the drift current due to the generation of EHP increased because of low potential barrier. The efficiency and fill factor were increased at the solar cell with increasing the diffusion process time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.722-725
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• 2012

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory based on a $0.35{\mu}m$ BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. The channel widths of a program transistor of the differential eFuse OTP cell are splitted into $45{\mu}m$ and $120{\mu}m$. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. It is confirmed by measurement results that the designed 8-bit eFuse OTP memory IP gives a better yield when the channel width is $120{\mu}m$.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.12
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• pp.769-776
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• 2016

In this study, a numerical simulation of a vanadium redox flow battery was investigated for reactions involving an electrochemical species using comprehensive conservation laws and a kinetic model. For a 3-D geometry of the cell, the distributions of electric potential, vanadium concentration, overpotential, and ohmic loss were calculated. The cell temperature and initial vanadium ion concentration were set as variables. The voltage and electrochemical loss were calculated for each variable. The effects of each variable's impact on the electrochemical performance of a vanadium redox flow battery was numerically analyzed using the calculated overpotential in the electrode and the ohmic loss in the electrolyte phase. The cell temperature increased from $20^{\circ}C$ to $80^{\circ}C$ when the voltage efficiency decreased from 89.34% to 87.29%. The voltage efficiency increased from 88.65% to 89.25% when the vanadium concentration was changed from $1500mol/m^3$ to $3000mol/m^3$.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1126_1127
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• 2009

태양전지모듈에 물리적 하중이 가해지면 전면유리의 연신율에 따라 모듈이 휘어지게 되고 이에 따라 내부에 열 봉합되어 있는 태양전지에 미세한 균열이 발생한다. 이 균열이 태양전지모듈의 단락전류 및 개방전압의 출력을 떨어뜨리는데 이는 균열로 인한 저항성분의 증가로 인한 것이다. 모듈내의 특정한 셀에서 미세균열(Micro-crack)의 발생은 출력의 저하, 셀 출력 Mismatch로 인한 모듈 내의 Hot-Spot발생, 균열로 인한 저항성분으로서의 열 발생과 같은 전체 태양전지모듈의 내구성을 저하시키는 요소로 작용한다. 본 연구에서는 결정질 태양전지 모듈의 출력에 영향을 미치는 요소 가운데 기계적 스트레스에 의한 미세균열(Micro-crack)이 전기적 출력에 미치는 영향에 대해 본 논문에서 알아보고자 한다.

• Journal of the Korean Society for Nondestructive Testing
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• v.31 no.1
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• pp.32-39
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• 2011

The object of this study is to evaluate and discriminate nondestructively the dislocation substructures of Cu and Cu-Zn alloy subjected to the low-cycle-fatigue. The ultrasonic wave velocity, electrical resistivity and positron annhilation lifetime(PAL) were measured to the nondestructive testing. Cyclic fatigue test of Cu and Cu-Zn alloy with much different stacking fault energies was conducted and the correlations between dislocation behavior and nondestructive parameters were studied. Dislocation cell substructure was developed in Cu, while planar array of dislocation structure was developed in Cu-35Zn alloy only increasing dislocation density with fatigue cycles. Decrease in ultrasonic wave velocity, increase in electrical resistivity and PAL were shown because of the development of lattice defects, dislocations and vacancies, by cyclic fatigue at room temperature. In contrast to Cu-Zn alloy of the planar-array dislocation substructure showing continuous changes in the nondestructive parameters, it does not make any noticeable changes in the nondestructive parameters after the evolution of dislocation cell substructure in Cu.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.2
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• pp.220-226
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• 2016

Because MS(Multi-Strand) cables consist of many strands, a jacking force is applied to each strand one by one for cable construction. All strands should have an equal tensile force when the last one is wedged. This is the core technology for MS iso-tensioning. In this study, a new MS cable iso-tensioning system was developed for controlling and jacking the high-strength strands, with an ultimate tensile strength of 2,200MPa, for a stay cable of extra-dosed/cable-stayed bridges. The newly developed iso-tensioning system consists of electrical resistance load cells, hydraulic jacking devices, hydraulic pumps, and integrated controllers. Moreover, it is embedded with an algorithm that can control and predict the variations in tensile forces of the Master and Slave strands in real time. Actual experiments were carried out to verify the function and performance of the newly developed system. This system was applied successfully to the stay cable construction of 2nd Tae-in extra-dosed bridge in Gwangyang.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.1
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• pp.69-74
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• 2021

This paper introduces a low-power voltage-controlled oscillator(VCO) with filters that consist of resistors and capacitors. The proposed VCO contains a 5-stage current mode buffer, and each buffer cell has a resistor-capacitor filter that connects input and output terminals. The filter adds a zero to the buffer cell. Because the zero moves the oscillation condition to high frequencies, the proposed VCO can generate a high frequency clock with low power consumption. The proposed circuit has been designed with 0.18 ㎛ CMOS process. The power consumption is 9.83 mW at 2.7 GHz. The proposed VCO shows 3.64 pJ/Hz in our simulation study, whereas the conventional circuit shows 4.79 pJ/Hz, indicating that our VCO achieves 24% reduction in power consumption.

• Korean Journal of Materials Research
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• v.9 no.11
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• pp.1075-1082
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• 1999

Composite air electrodes of 50/50 vol% LSM- YSZ where LSM =$\textrm{La}_{1-x}\textrm{Sr}_{x}\textrm{MnO}_{3}$(0$\leq$x$\leq$0.5) were prepared by colloidal deposition technique. The electrodes were then examined by scanning electron microscopy (SEM) and studied by ac impedance spectroscopy in order to improve the performance of a solid oxide fuel cell (SOFC). Reproducible impedance spectra were confirmed by using the improved cell, consisting of LSM- YSZ/YSZ/LSM-YSZ. These spectra were a strong function of operating temperature and the stable conditions for the cells were typically reached at $900^{\circ}C$. The typical spectra measured for an air//air cell at $900^{\circ}C$ were composed of two arcs. Addition of YSZ to the LSM electrode led to a pronounced decrease in cathodic resistivity of LSM-YSZ composite electrodes. Polishing the electrolyte surface to eliminate the influences of surface impurities could further reduce cathode resistivity. The cathodic resistivity of the LSM-YSZ electrodes with catalytic interlayer (Ni or Sr) was much smaller than that of LSM-YSZ electrodes without catalytic interlayer. In addition, the cathodic resistivity of the LSM-YSZ electrodes was a strong function of composition of electrode materials, the electrolyte geometry, and applied current.