• Annual Conference of KIPS
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• 2001.10a
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• pp.489-492
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• 2001

소프트웨어의 대형화와 급격히 변화하는 소프트웨어 시장에 시기 적절히 대응하기 위해, 기존의 소프트웨어를 재사용함은 물론이고 재사용이 용이한 구조로 소프트웨어를 구성하여 다른 부분에 영향을 미치지 않고 특정 부분을 변경시킬 수 있는 솔루션이 요구된다. 이러한 기술에 부합되는 것이 재사용성, 대체가능성 등의 기능을 강조한 컴포넌트 기술이라 할 수 있겠다. 컴포넌트 기반 시스템을 설계하는데 있어서는 기존의 객체지향 접근방식을 포함하면서 컴포넌트의 고유의 특성을 반영하는 다른 접근방식을 필요로 하게 된다. 본 논문에서는 이러한 객체지향적 접근방식에 개념적인 컴포넌트 설계 방식과 이를 EJB 컴포넌트로 다시 상세화하는 컴포넌트의 모텔링 프로세스와 이를 지원하는 도구에 대해 다룬다.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.996-998
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• 2005

전기철도나 지하철 분야에 사용되고 있는 고속 DC 차단기의 조작부는 solenoid actuator 방식이나 motor charging 방식을 주로 채택하고 있으나 구조가 복잡하고 부품수가 많아 부피가 크다는 단점이 있다. 이에 반해 magnetic actuator 방식은 동작시간과 제어가 용이하고 부품수가 감소하여 신뢰성과 반복성이 뛰어나다. 본 논문에서는 고속 DC 차단기 조작부를 영구자석 엑추에이터(PMA)방식으로 적용하고자 영구자석(PM)의 개략적 설계 및 이를 이용한 PMA 설계를 하였고, 유한요소 해석을 통해 이들의 동작특성을 해석하였다.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1218-1219
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• 2011

본 논문은 KA555 Timer을 이용한 PWM회로로 구성된 아날로그 방식의 DC-DC Buck Converter와 AVR ATmega128를 이용한 PWM회로로 구성된 디지털 방식의 Buck Converter을 설계하여 각각의 특성을 비교 분석하였다. 제안된 컨버터들은 공통적으로 전원을 공급받아 전압분압회로를 통해 DC-DC Buck Converter의 PWM 제어회로부에 공급되며, 아날로그방식 컨버터의 제어부는 KA555 timer을 이용하여 구형파회로와 미분회로를 구성하고, 출력된 삼각파와 정현파를 KA555 timer을 이용하여 PWM파형으로 제어한다. 디지털방식의 컨버터는 AVR RISC 8-bit 마이크로프로세서 ATmega128을 이용하여 PWM 제어부를 구성하고 이를 LCD창을 통해 그 값을 확인할 수 있도록 설계하였다. 본 논문에서는 두 가지 방식의 제어부를 구성하여 제작 및 실험함으로써, 각각의 장단점을 비교하여 시스템 구성시 요구조건인 소형경량, 단가저감, 효율 등을 비교하여 그 상황에 맞는 설계가 가능할 것이다.

• Tunnel and Underground Space
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• v.33 no.6
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• pp.435-444
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• 2023

In the licensing application for the deep geological disposal system of high-level radioactive waste in Finland, the disposal tunnel backfilling has been changed from the block/pellet (for the construction) to the granular type (for the operation). Accordingly, for establishing the design concept for backfilling, it is necessary to examine applicability to the domestic facility through analyzing problems of the existing method and improvements in the alternative design. In this paper, we first reviewed the principal studies conducted for changing the backfill method in the licensing process of the Finnish facility, and identified the expected problems in applying the block/pellet backfill method. In addition, we derived the evaluation factors to be considered in terms of technical and operational aspects for the backfilling solution, and then conducted a comparative analysis for two types of backfill methods. This analysis confirmed the overall superiority of the design change. It is expected that these results could be utilized as the technical basis for deriving the optimum design plan in development process of the Korean-specific deep disposal facility. However, applicability should be reviewed in advance based on the latest technical data for the detailed evaluation factors that must be considered for selecting the backfilling method.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.112-118
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• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• Convergence Security Journal
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• v.6 no.4
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• pp.83-90
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• 2006

In this paper, we propose a new design method for a robust vector quantizer that is independent of the statistical characteristics of input images in the wavelet transformed image coding. The conventional vector quantizers have failed to get quality coding results because of the different statistical properties between the image to be quantized and the training sequence for a codebook of the vector quantizer. Therefore, in order to solve this problem, we used a pseudo image as a training sequence to generate a codebook of the vector quantizer; the pseudo image is created by adding correlation coefficient and edge components to uniformly distributed random numbers. We will clearly define the problem of the conventional vector quantizers, which use real images as a training sequence to generate a codebook used, by comparing the conventional methods with the proposed through computer simulation. Also, we will show the proposed vector quantizer yields better coding results.

• Korean Journal of Construction Engineering and Management
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• v.8 no.5
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• pp.119-131
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• 2007

Design build (DB) is a construction project delivery system which has become one of the favored ones and the growth of DB by the public agencies has been steadily increasing. DB can be viewed as an evolutionary project delivery system, since DB project team members collaborate on work with each other, keep seeking cost effective and innovative alternatives that meet the construction needs of the project. Thus DB outperformed others in delivery speed, cost saving, and turnover quality. In Korea, DB projects likewise have steadily increased that it is needed to analyze characteristics of DB delivery system in Korea. For that purpose, this research would offer an analysis of characteristics of DB delivery system in Korea using system dynamics model with investigating the public market trend, comparing DB performance to DBB, and analyzing questionnaire survey.

• Korean Journal of Construction Engineering and Management
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• v.8 no.2
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• pp.75-83
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• 2007

Recently, the Design-Build (DB) delivery method in public sector makes some argument by reason of the initial cost which is more higher than those of Design-Bid-Build (DBB). According to the results of pervious researches related to the performance evaluation of delivery method, DB can lead the reduction of project cycle time and also is superior to the traditional DBB in terms of construction quality. The performance on each delivery method could be generally evaluated by a project cost and a project cycle time as one of quantitative analyses, and also by construction quality as one of qualitative analyses. In most researches, the evaluation of performance level based on delivery methods has been evaluated by the degree of their satisfaction through the interview with owners. Therefore, this paper analyzed the design documents of construction projects delivered by traditional DBB and DB in bridge construction projects in order to measure design quality, constructability, maintainability, and etc. As an above-mentioned analyses, finally, this research shown that how much the difference of performance level is by each delivery method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.36-41
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• 2006

In this paper, we present the performance of iterative decoding with a Turbo decoder and a M-ary QAM(Quadrature Amplitude Modulation) demapper. The demappers are designed with Max-Log-MAP algorithm and it's approximated one. In addition, we provide implementing block for the approximated algorithm. From the results of computer simulations, the approximated algorithm of the Max-Log-MAP has little bit worse than the Max-Log-MAP but suggests low complexity for practical implementation.