• Proceedings of the Korea Multimedia Society Conference
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• 2003.11b
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• pp.933-936
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• 2003

본 논문은 비트 매트릭스(bit matrix) 확률 모델과 이를 입력으로 사용하는 개량된 이진 산술부호 알고리즘을 제안한다. 비트들로 이루어진 비트 평면에서 3$\times$3 비트 매트릭스를 정의하였다. 그리고 비트 평면을 조사하여 2연속 혹은 3연속 비트 매트릭스들에 대한 확률모델을 구하였다. 본 연구에서는 3 가지의 확률간격(interval)을 가지는 개량된 이진 산술부호기률 사용하였다. 개량된 이진 산술부호 알고리즘의 장점은 구조가 간결하고 또한 부호화가 진행되는 도중에 결과 비트스트림을 생성하는 특징이 있다. 이진 산술부호기는 2연속 혹은 3연속 비트매트릭스를 입력하여 산술부호화를 수행하도록 한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.6
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• pp.550-559
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• 2005

The matrix converter provides sinusoidal input and output wave forms, bidirectional power flow, controllable input power factor and a long life, compared to the VSI(Voltage Source Inverter) with diode rectification stage at the input. However it has tasks, such as complexity of the control method, ride-through problem and low voltage-ratio limitation, to overcome for commercializing, This paper describes the design, construction and implementation of matrix converter based on space vector modulation technique. The implemented prototype of matrix converter is built using the exclusive IGBT module and control circuit constituted with DSP and CPLD and it has an input filter, overvoltage protection circuit and commutation means for overcoming practical issues. The good results tested using an induction motor are also presented.

• Journal of the Society of Naval Architects of Korea
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• v.29 no.1
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• pp.143-157
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• 1992

For the design of structural systems having the prescribed or optimum dynamic characteristics, some design changes of the initially designed system are required. In these cases, if the sensitivity analysis which can predict the changes of dynamic characteristics due to the changes of design variables is applied, the design changes can be carried out rationally and very efficiently. For many structural systems, it is well known that the analysis by the transfer matrix method(TMM) and the combined finite element-transfer matrix method(FETMM) is more efficient than the analysis by the finite element method. However, most known studies on the sensitivity analysis of structural systems premise using the finite element method. In this paper, the sensitivity analysis methods by the TMM and the FETMM are presented and some numerical investigations on the beam-column with elastically restrained ends and intermediate contraints and the stiffened plate having subsystems are carried out. The results of the numerical examples show good accuracy and computational efficiency of the presented methods, and show that the application of sensitivity analysis in the dynamic characteristic reanalysis give good results within the practically changeable range of design variables.

• Journal of the Korean Society for Railway
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• v.11 no.1
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• pp.26-32
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• 2008

This paper discusses WBS (Work Breakdown Structure) that is known for technique of basic project management. The WBS use in domestic industries often exhibit errors in Its structure. The most common serious error is space-oriented breakdown structure of PBS (Product Breakdown Structure) that becomes the core element of the WBS. This paper proposes a method to correct the problem of space-oriented breakdown structure constructed in domestic railroad industry. DSM method was adopted to construct PBS containing function-oriented structure. The proposed process and method will contribute to minimize time that take to construct an accurate and useful PBS.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.527-539
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• 2008

This paper presents a performance estimation technique based on queuing analysis for on-chip bus matrix architectures of Multi-Processor System-on-Chips(MPSoCs). Previous works relying on time-consuming simulation are not able to explore the vast design space to cope with increasing time-to-market pressure. The proposed technique gives accurate estimation results while achieving faster estimation time than cycle -accurate simulation by order of magnitude. We consider the followings for the modeling of practical memory subsystem: (1) the service time with the general distribution instead of the exponential distribution and (2) multiple-outstanding transactions to achieve high performance. The experimental results show that the proposed analysis technique has the accuracy of 94% on average and much shorter runtime ($10^5$ times faster at least) compared to simulation for the various examples: the synthetic traces and real-time application, 4-channel DVR.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.6
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• pp.501-504
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• 2017

In this paper, a hybrid beamforming antenna system using broadband butler matrix and phase shifter is proposed. In the previous works, an $8{\times}8$ butler matrix is used to overcome a drawback of the $4{\times}4$ butler matrix based switched beamforming which provides only 4 beam patterns. However the $8{\times}8$ butler matrix should be designed on the bi-layered substrate using via holes due to its complex structure. It causes performance degradation. To overcome these problems, the proposed hybrid beamforming antenna system is designed on the single side of the substrate for simple structure. By addition of two phase shifter, it provide various beam patterns. The proposed antenna system provides more than 10 dBi radiation gain in the ${\pm}45^{\circ}$ scanning range by 16 input combinations.

• Proceedings of the KAIS Fall Conference
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• 2010.05a
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• pp.18-23
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• 2010

4$\times$4 Butler Matrix structure has been presented in this paper. It can passes the signal with equal power level and phase difference in the 824MHz to 894MHz frequency of the cellular band. Conventional Butler Matrix was implemented as a single layer substrate structure, but in this paper, we use multi-layer substrate structure and eventually we could get it reduced in size than others. We also used the LTCC coupler to reduce the size effectively, instead of using $90^{\circ}$ hybrid coupler composed of microstrip structure. we used Designer V3.5 Ansoft HFSS V11 for design of 4$\times$4 Butler matrix. Finally, we get good agreements between simulation and experimental results.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.10-21
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• 1999

This paper describes a 12bit CMOS current cell matrix D/A converter which shows a conversion rate of 65MHz and a power supply of 3.3V. Designed D/A converter utilizes current cell matrix structure with good monotonicity characteristic and fast settling time, and it is implemented by using the tree structure bias circuit, the symmetrical routing method with ground line and the cascode current switch to reduce the errors of the conventional D/A converter caused by a threshold voltage mismatch of current cells and a voltage drop of the ground line. The designed D/A converter was implemented with a $0.6{\mu}m$ CMOS n-well technology. The measured data shows a settling time of 20ns, a conversion rate of 50 MHz and a power dissipation of 35.6mW with a single power supply of 3.3V. The experimental SNR, DNL, and INL of the D/A converter is measured to be 55dB, ${\pm}0.5LSB$, and ${\pm}2LSB$, respectively.

• Proceedings of the Optical Society of Korea Conference
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• 1991.06a
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• pp.22-22
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• 1991

광의 병렬처리 능력을 잘 활용한 1$\times$4 매트릭스 스위치의 구조와 전극구조를 설계하고 스위치 특성을 조사하기 위하여 beam propagation method(BPM)를 이용하여 수치계산을 하였다. 기존의 매트릭스 스위치는 대부분의 경우 방향성 결합기를 스위치 element로 이용하여 왔으나 이 결합기는 소자의 길이가 길기 때문에 단일 LinBO3 웨이퍼상에 집적할 수 있는 매트릭스 스위치의 크기가 제한되는 단점이 있다. 본 연구에서는 두 도파로 사이에 세 번째 도파로를 삽입하여 두 도파로를 결합시키는 세 도파로 결합기를 스위치 element로 사용하여 세 개의 스위치 element를 LiNbO3기판위에 직렬로 집적시킨 1$\times$4 매트릭스 스위치를 구성하였다. 스위치 element와 1$\times$4 매트릭스 스위치를 구성하였다. 스위치 element와 1$\times$4 매트릭스 스위치의 특성을 BPM을 사용하여 수치계산할 때 단일 모드 도파로의 유효 굴절을 분포는 n(X) = nm + $\Delta$ncosh-2(2x/w)의 형태로 가정했으며, 사용된 파라미터의 값은 각각 nm=2.1455, $\Delta$n=0.003, W=5$mu extrm{m}$, d=5$\mu\textrm{m}$, λ=1.3$\mu\textrm{m}$ 이고 S-파라메터의 값은 0.95927이므로 단일 모드 도파로가 된다. 계산결과 스위치 element의 결합길이는 3810$\mu\textrm{m}$이며 도파로의 길이가 결합길이와 같을 때 전극에 인가된 전압에 의한 도파로의 굴절을 섭등의 함수로 출력광의 세기를 계산한 결과 스위칭 전압은 14.85volt이고 crosstalk는 -18.9dB였다. 이 스위치 element로 구성된 1$\times$4 매트릭스 스위치는 스위칭 전압을 세 개의 전극에 적절한 조합으로 인가함으로써 한 입력 도파로에 결합된 광이 내개의 출력 도파로중 한 도파로에 스위칭 된다. 한편 수치계산의 결과를 실험적으로 확인하기 위해 스위치 element와 1$\times$4 매트릭스 스위치를 z-cut의 LinbO3 결정에 Ti을 열확산시켜 제작한 소자의 스위칭 특성을 발표할 예정이다.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.