• Title/Summary/Keyword: 설계마진

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An Auto-tuning Algorithm of PI Controller Using Time Delay Element (시간 지연 요소를 이용한 PI 제어기 자동 동조 알고리즘)

  • Oh, Seung-Rohk
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.47 no.6
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    • pp.1-5
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    • 2010
  • We propose an algorithm which can classify the system should use a PI controller, which have a weak high frequency attenuation characteristics near the critical frequency. To classify the system, we use a time delay element to calculate a gain attenuation rate near the critical frequency. The proposed algorithm also can design PI controller with the given magnitude margin and phase margin specification. The proposed algorithm uses time delay element and saturation function to identify the one point information in frequency domain. We justify the proposed algorithm via the simulation.

A Study on Centrifugal Compressor Design Optimization for Increasing Surge Margin (서지 마진 증가를 고려한 원심 압축기 설계 최적화)

  • Chai, Jae-Ha
    • The KSFM Journal of Fluid Machinery
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    • v.11 no.2
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    • pp.38-45
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    • 2008
  • This study presents a numerical procedure to optimize the compressor design to increase the surge margin of compressor with response surface method (RSM). The Box-Behnken design method is used to reduce the number of calculation for fitting the second-order response surface. In order to consider the increase of surge margin during numerical optimization without any calculation at the surge point, the slope of compressor characteristic curve at the design point is suggested as an objective function in the present optimization problem. Mean line performance analysis method is used to get the design and off-design characteristic curves of centrifugal compressor. The impeller exit angle, impeller exit height and impeller radius are chosen as design variables. The optimum shapes show the increase of surge margin for the surge margin optimization and increase of efficiency for the efficiency optimization in comparison with an initial shape.

Influence of Parasitic Resistances and Transistor Asymmetries on Read Operation of High-Resistor SRAM Cells (기생저항 및 트랜지스터 비대칭이 고저항 SRAM 셀의 읽기동작에 미치는 영향)

  • Choi, Jin-Young;Choi, Won-Sang
    • Journal of IKEEE
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    • v.1 no.1 s.1
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    • pp.11-18
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    • 1997
  • By utilizing the technique to monitor the DC cell node voltages through circuit simulation, degradation of the static read operating margin In high load-resistor SRAM cell was examined, which is caused by parasitic resistances and transistor asymmetries in this cell structure. By selectively adding the parasitic resistances to an ideal cell, the influence of each parasitic resistance on the operating margin was examined, and then the cases with parasitic resistances in pairs were also examined. By selectively changing the channel width of cell transistors to generate cell asymmetry, the influence of cell asymmetry on the operating margin was also examined. Analyses on the operating margins were performed by comparing the supply voltage values at which two cell node voltages merge to a single value and the differences of cell node voltages at VDD=5V in the simulated node voltage characteristics. By determining the parasitic resistances and the transistor asymmetries which give the most serious effect on the static read-operation of SRAM cell from this analysis based on circuit simulated, a criteria was provided, which can be referred in the design of new SRAM cell structures.

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A Voltage Binning Technique Considering LVCC Margin Characteristics of Different Process Corners to Improve Power Consumption (공정 코너별 LVCC 마진 특성을 이용한 전력 소모 개선 Voltage Binning 기법)

  • Lee, Won Jun;Han, Tae Hee
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.7
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    • pp.122-129
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    • 2014
  • Due to remarkable market growth of smart devices, higher performance and more functionalities are required for a core system-on-chip (SoC), and thus the power demand is rapidly increasing. However, aggressive shrink of CMOS transistor have brought severe process variations thereby adversely affected the performance and power consumption under strict power constraint. Voltage binning (VB) scheme is one of the effective post silicon tuning techniques, which can reduce parametric yield loss due to process variations by adjusting supply voltage. In this paper, an optimal supply voltage tuning based voltage binning technique is proposed to reduce average power without an additional yield loss. Considering the different LVCC margins of process corners along with speed and leakage characteristics, the proposed method can optimize the deviation of voltage margin and thus save power consumption. When applying on a 30nm mobile SoC product, the experimental results showed that the proposed technique reduced average power consumption up to 6.8% compared to traditional voltage binning under the same conditions.

Design and Development of DSSS Modem for UAV Uplink (무인기용 상향링크 대역확산 송수신기 설계 및 개발)

  • Gim, Jong-Man;Eun, Chang-Soo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.8
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    • pp.1-9
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    • 2009
  • In this paper, we describe DSSS transceiver development robust to jamming signals as an investigation of ECCM transceiver for UAV uplink. The jamming margin is 15dB or greater with the development target of transceiver because the jamming margin is more important than the transmission rate of data and the spreading code can be changeable. The rake receiver is applied to combine multipath components and turbo code which the coding gain is 7.2dB as a FEC. In this paper, the whole structure, design method and functional test result about the designed modem are described and a conclusion is made.

Radio transmission link design based on a test bed considering a multi-beam active phase array antenna (다중빔 능동위상배열 안테나를 고려한 테스트베드 기반 Radio 전송링크 설계)

  • Youn, Jong-Taek;Kim, Yongi;Park, Hongjun;Park, Juman
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.11
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    • pp.1574-1580
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    • 2021
  • This paper designs and presents the results of an air network simulation radio transmission link applied with a multi-beam active phase array antenna simulator in a testbed system for verifying an air network currently underway as a technology development task. Using the Ku band, the Radio transmission link was designed in consideration of the link budget to satisfy the requirements for the system being developed. Considering short-distance links and long-distance links, the required EIRP and G/T performance scales of multi-beam repeaters and mission planes were applied to confirm the minimum and maximum link margins based on Eb/No. In this Radio Transmission Link design, the application analysis results such as rainfall availability are used to effectively establish standards when selecting the operating radius of the multi-beam relay system and related system standards.

Design of Current Controller for an Induction Motor using Robust Stability Theory (강인안정도 기법을 이용한 유도전동기의 전류 제어기 설계)

  • 박태식;유지윤
    • The Transactions of the Korean Institute of Power Electronics
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    • v.8 no.2
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    • pp.165-172
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    • 2003
  • In this paper, the new robust current control scheme is proposed for an Induction motor. The proposed design scheme of current controller tan obtain a specified stability margin through electrical parameter variation by using Kharitonov robust stability theory. The characteristics of the proposed design scheme are compared with those of a conventional scheme by computer simulation and its effectiveness and usefulness is verified by experiments on the 0.75kW induction motor drive.

Low Power 4-Gb/s Receiver for GND-referenced Differential Signaling (접지기반 차동신호 전송을 위한 저전력 4-Gb/s 수신단 설계)

  • Lee, Mira;Kim, Seok;Jeong, Youngkyun;Bae, Jun-Han;Kwon, Kee-Won;Chun, Jung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.9
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    • pp.244-250
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    • 2012
  • This paper describes a 4-Gb/s receiver circuit for a low-swing ground-referenced differential signaling system. The receiver employs a common-gate level-shifter and a continuous linear equalizer which compensates inter-symbol-interference (ISI) and improves voltage and timing margins. A bias circuit maintains the bias current of the level-shifter when the common level of the input signal changes. The receiver is implemented with a low-power 65-nm CMOS technology. When 4-Gb/s 400mVp-p signals are transmitted to the receiver through the channel with the attenuation of -19.7dB, the timing margin based on bit error rate (BER) of $10^{-11}$ is 0.48UI and the power consumption is as low as 0.30mW/Gb/s.

세기조절방사선치료 조사면의 최소 조각 크기에 대한 치료중 표적 움직임의 효과

  • 서예린;이병용;안승도;이상욱;김종훈;신성수;신승애;최은경
    • Proceedings of the Korean Society of Medical Physics Conference
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    • 2003.09a
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    • pp.37-37
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    • 2003
  • 목적 : 일반적으로 세기조절방사선치료 조사면의 작은 조각 크기에 대해, 이상적인 플루언스 지도 혹은 치료계획장치로부터의 최적화된 결과에 가까운 선량분포에서 더 좋은 leaf sequence를 얻을 수 있다. 한편, 치료중 장기의 움직임이 가장 작은 조각 크기의 선택을 방해하는 문제는 항상 존재한다. 게다가, 전통적인 정지 조사면과 달리 표적이 움직이는 동안 조사면 자체도 움직이므로 움직이는 표적에 대한 세기조절방사선치료의 경우에서 적절한 표적 마진에 관한 질문이 제기되어왔다. 따라서, 이 연구에서는 조각 크기에 대한 치료중 표적 움직임의 효과를 연구하였다. 대상 및 방법 : 세기조절방사선치료 플루언스 지도에 대해, 다양한 크기 - 0.5$\times$0.5, 1.0$\times$1.0, $1.5\times$1.5, 2.0$\times$2.0, 3.0$\times$3.0, 4.0$\times$4.0, 5.0$\times$5.0 $ extrm{cm}^2$ - 의 정사각형 패턴들을 설계하였고, Leaf sequence 는 step-and-shoot 빔 전달 방법을 이용하였다. 인접 조각들 사이의 세기 비율은 0.2, 0.4, 0.6, 0.8, 1.0로 하였고, 표적 움직임은 범위가 0.5-2.0 cm인 사인곡선 형태로 가정하였다. 움직임 묘사를 위해 동적 leaf 의 움직임이 표적의 움직임 을 반영하도록 계산되었고 움직임의 효과를 분석하기 위해 필름선량측정을 수행하였다. 결과 : 인접 조각의 세기 비율은 모든 경우에서 저하되었고, 호흡 진폭의 반보다 작은 조각 크기에 대한 선량분포는 임상적으로 유의할만큼 저하된 세기 지도를 보였다. 조각에 대해 방사선 조사시간의 두 호흡주기이상에 대해서는, 표적 마진 주위의 선량분포가 통상적인 정지 조사면에서와 같았다. 결론 : 플루언스 지도에서 세기조절방사선치료 조각의 최소 크기는 치료중 장기 움직임을 고려한 후 선택되어야 한다. 조각에 대한 방사선 조사시간의 두 호흡주기이상에 대해서는, 표적 마진을 기존의 정지 조사면과 같게 정의할 수 있었다.

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