• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.385-390
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• 2013

This paper proposes an efficient hardware architecture of CABAC for HEVC decoder. The proposed method is structured to handle two bins in one cycle, while preserving data dependencies of the CABAC. In addition, the processing time of the proposed architecture is reduced because the operation using Offset and Range is processed while the architecture reads rLPS from rLPSROM. As a result of analyzing operating frequency of the proposed CABAC architecture, the proposed architecture has improved by 40% than the previous one.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2574-2576
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• 2004

본 논문에서 디지털 영상의 인증과 무결성을 확인하는 새로운 워터마킹 기법을 제안하였다. 컨텐츠에 대한 인증과 무결성을 체크하는 방법 중, 암호학적 해쉬함수(MD5)를 이용한 Wong의 방법이 인증과 무결성을 위한 워터마크 방법으로는 가장 적합하다. 특히 이 방법은 암호학적인 해쉬함수를 사용하므로 워터마킹 알고리즘의 안정성이 암호학적 해쉬함수의 안정성에 의존하게 되므로 안전하다. 해쉬 값을 계산하려면 법(modulus), 보수 (complement), 시프트 (shift), XOR (bitwise exclusive-or) 등 연산이 필요하다. 그러나 본 논문에서는 곱셈 연산만 필요로 한 산술부호화기법 (Arithmetic coding)을 이용하였다. 이 기법은 입력되는 심벌 (symbol)들의 확률구간을 계속적으로 곱하여 결과적으로 얻어지는 누적확률구간을 출력한다. 본 논문에서 키(key) 값에 의하여 심벌들의 확률구간을 결정하고, 그리고 키 값에 의하여 심벌들의 입력순서론 재배치함으로써 결과적으로 얻어지는 누적확률 값은 키 값에 의존하게 하였다. 실험을 통하여 본 알고리즘이 무결성을 입증할 수 있고, PSNR은 51.13dB 이상으로서 아주 좋으며, 위변조를 판단하는데 소요되는 시간은 해쉬함수 (MD5)를 사용하는데 걸리는 시간이 1/3배이다. 그러므로 실시간으로 사용 가능하다.

• Journal of Korea Multimedia Society
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• v.7 no.5
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• pp.658-667
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• 2004

For digital image compression, various fractal image coding schemes using the self-similarity of image have been studied extensively. This paper discusses the problem that occurs during the calculating process of adaptive orthogonal transformation and provides improvements of LIFS coding scheme using the transformation. This proposed scheme has a better performance than JPEG for a wide range of compression ratio. This research also proposes an image composition method consisting of all domains of the transformation. The results show that the arithmetic operation processes of the encoder and the decoder become much smaller even without the distortion of the coding performance.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.1515-1518
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• 2009

최적정규기저(Optimal Normal Basis)를 이용한 $GF(2^m)$상의 곱셈은 ECC(Elliptic Curve Cryptosystems: 타원곡선 암호시스템) 및 유한체 산술 연산의 하드웨어 구현에 적합하다는 것은 잘 알려져 있다. 본 논문에서는 최적정규기저의 하드웨어적 장점을 이용하여 합성체(Composit Field)상의 곱셈기를 제안하며, 기존에 제안된 합성체상의 곱셈기와 비교 및 분석한다. 제안된 곱셈기는 최적정규기저 타입 I, II의 대칭성과 가수의 중복성을 이용한 열벡터의 재배열에 따른 XOR 연산의 재사용으로 낮은 하드웨어 복잡도와 작은 지연시간을 가진다.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.327-336
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• 2007

Lots of effort toward design optimizations have been paid for a cost-effective system design in various ways from a transistor level to RTL designs. In this paper, we propose a bit level optimization of an adder design for expanding its design space. For the bit-level optimization, a heterogeneous adder organization utilizing a mixture of carry propagation schemes is proposed to design a delay-area efficient adder which were not available in an ordinary design space. Then, we develop an optimization method based on Integer Linear Programming to search the expanded design space of the heterogeneous adder. The novelty of the Proposed architecture and optimization method is introducing a bit level reconstruction/recombination of IPs which have same functionality but different speed and area characteristics for producing more find-grained delay-area optimization.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.2
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• pp.224-229
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• 2005

Generally, genetic algorithm (GA) has too much time and space complexity when it is running in the typical processor. Therefore, we are forced to use the high-performance and expensive processor by this reason. It also works as a barrier to implement real device, such a small mobile robot, which is required only simple rules. To solve this problem, this paper presents and proposes enhanced processor-architecture for the faster GA processing. A typical processor architecture can be enhanced and specialized by two approaches: one is a sorting network, the other is a residue number system (RNS). A sorting network can improve the time complexity of which needs to compare the populations' fitness. An RNS can reduce the magnitude of the largest bit that dictates the speed of arithmetic operation. Consequently, it can make the total logic size smaller and innovate arithmetic operation speed faster.

• The KIPS Transactions:PartC
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• v.17C no.2
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• pp.145-152
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• 2010

In this paper, we first propose a fast division algorithm in GF($2^{163}$) using standard basis representation, and then it is mapped into divider for GF($2^{163}$) with iterative hardware structure. The proposed algorithm is based on the binary ExtendedGCD algorithm, and the arithmetic operations for modular reduction are performed within only one "while-statement" unlike conventional approach which uses two "while-statement". In this paper, we use reduction polynomial $f(x)=x^{163}+x^7+x^6+x^3+1$ that is recommended in SEC2(Standards for Efficient Cryptography) using standard basis representation, where degree m = 163. We also have implemented the proposed iterative architecture in FPGA using Verilog HDL, and it operates at a clock frequency of 85 MHz on Xilinx-VirtexII XC2V8000 FPGA device. From implementation results, we will show that computation speed of the proposed scheme is significantly improved than the existing two approaches.

• Journal of Broadcast Engineering
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• v.20 no.2
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• pp.224-237
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• 2015

In this paper, we introduce the fast decoding method with the SIMD (Single Instruction Multiple Data) instructions for HEVC RExt (High Efficiency Video Coding Range Extensions). Several tools of HEVC RExt such as intra prediction, interpolation, inverse-quantization, inverse-transform, and clipping modules can be classified as the proper modules for applying the SIMD instructions. In consideration of bit-depth increasement of RExt, intra prediction, interpolation, inverse-quantization, inverse-transform, and clipping modules are accelerated by SSE (Streaming SIMD Extension) instructions. In addition, we propose effective implementations for interpolation filter, inverse-quantization, and clipping modules by utilizing a set of AVX2 (Advanced Vector eXtension 2) instructions that can use 256 bits register. The evaluation of the proposed methods were performed on the private HEVC RExt decoder developed based on HM 16.0. The experimental results show that the developed RExt decoder reduces 12% average decoding time, compared with the conventional sequential method.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.51-58
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• 2004

Most of pubic-key cryptosystems are built on the basis of arithmetic operations defined over the finite field GF$GF(2^m)$ .The other operations of finite fields except addition can be computed by repeated multiplications. Therefore, it is very important to implement the multiplication operation efficiently in public-key cryptosystems. We propose an efficient bit-parallel normal basis multiplier for$GF(2^m)$ fields defined by All-One Polynomials. The gate count and time complexities of our proposed multiplier are lower than or equal to those of the previously proposed multipliers of the same class. Also, since the architecture of our multiplier is regular, it is suitable for VLSI implementation.

• Journal of Korea Society of Industrial Information Systems
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• v.23 no.4
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• pp.13-22
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• 2018

In this paper, double encryption technology of image based on scramble operation and phase-shifting digital holography is proposed. For the purpose, we perform first encryption digitally using scramble operation for the to be encrypted image, and perform phase modulation to the first encrypted image. Finally, we get the secondary encryption information through the interference between the phase-shifted reference wave and phase modulated image. The decryption process proceeds in the reverse order of the encryption process. The original image is reconstructed by digitally decoding the two encrypted images through a phase shift digital holography technique that appropriately performs arithmetic processing, phase-demodulating and then using the encryption key information used in the scramble operation. The proposed cryptosystem can recover the original image only if both the key information used in the scramble operation, the distance information used in the phase shift digital holography technique, and the wavelength of the light source are known accurately.