• The Korean Journal of Rheology
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• v.4 no.2
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• pp.116-126
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• 1992

본 연구에서는 형내압 파형제어 시스템, 초고속, 사출성형, 그리고 금형진공 시스템 등을 갖춘 사출 성형기를 이용하여 정밀 구면렌즈를 성형하기 위한 실험을 수행하였다. 이 러한 목적을 위해 성형공정 변수인 사출시간 충전압력 그리고 보압시간이 성형품에 미치는 영향을 중량과 곡률반경 구면 정밀도 그리고 구면오차의 간접무늬를 측정하여 연구하였다. 그결과로서 성형품의 중량(칫수)과 곡률반경에 지대한 영향력을 행사하는 변수는 충전압력 이며 사출시간과 보압시간은 곡률반경과는 무관해 보이고 중량의 증가에는 기여하지만 공정 사이클 시간을 증가시키는 문제가 지적된다. 구면정밀도 측정실험 결과 길지도 짧지도 않는 15∼20초 사이의 보압시간 4초이내의 빠른 사출시간 그리고 860kg/cm2 이상의 높은 충전압 력에서 우수한 결과를 보여주었다, 마지막으로 구면의 형상에 대한 간접무늬 측정결과는 성 형공정을 이해하는데 강력한 도구가 됨을 발견하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.1
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• pp.9-16
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• 2016

Since most of devices in the IEEE 802.15.4 LR-WPAN are expected to operate on batteries, they must be designed to consume energy in a very conservative way. Two energy conservation algorithms are proposed for the LR-WPAN: DDC (Dynamic Duty Cycle) and DBT (Dynamic Beacon Tracking). The DDC algorithm adjusts duty cycle dynamically depending on channel conditions. The DBT algorithm switches beacon tracking mode on and off adaptively depending on traffic conditions. Combining the two algorithms reduces energy consumption more efficiently for a wide range of input loads, while maintaining frame delivery ratio and average delay at satisfactory levels.

• Journal of Fashion Business
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• v.19 no.4
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• pp.1-20
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• 2015

Acceleration of the fashion cycle has caused problems of environmental pollution because consumers made a lot of waste of clothes. To solve them, upcycle design has been uprised. This study researched the present condition through recent cases of upcycle design. The standard of collected cases is focused on used products which was already run out once and then has been recreated by being recreated with new design. Through this study, there is a purpose to provide solution of environmental pollutions and a right direction of upcycle fashion design. Collected cases are classified into five production methods. First method is Melting and Compressing, which it melts or compresses materials. Second method is Gathering and Combining, which it gathers or combines each different materials. Third method is Cutting and Dividing, which it cuts or divides products materials. Fourth method is Mixing and Changing, which it mixes materials, adds design elements, and changes of purpose. Final things are classified with multiplicatively used factors which are already divided.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.78-83
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• 2014

This paper suggest an effective idea to implement an low area multi-mode one dimension transform block of HEVC(High Efficiency Video Coding). The time consuming multiplier path is designed to operate on low frequency. Normal multipliers dealing with variable operands are replaced with smaller constant multipliers which do the product with constant coefficient and variable only using shifters and adders. This scheme increases total multiplier counts but entire areas are reduced owing to smaller area of constant multiplier. Idle cycles caused by doubled multipliers enable to use multi-cycle paths on the cycle eating multiplier data path. Operating frequency is lowered by multi-cycle path but total throughput is maintained. This structure is implemented with TSMC 0.18 CMOS process library, and operated on 186MHz frequency to process a 4k($3840{\times}2160$) image. Max operating frequency is 300MHz.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• Journal of the Korean Society of Propulsion Engineers
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• v.20 no.3
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• pp.1-8
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• 2016

It was examined that start-up characteristics of a staged combustion cycle engine powerpack. Among various parameters, valve opening time was considered as a main factor affecting the start-up characteristics. Using monte-carlo method, characteristics variation was analyzed when the valve opening time deviates from the nominal value. As a result, the main fuel valve opening time and the start turbine ending time were significant associated with the startup characteristics. When separating main fuel valve opening time and start turbine stop time, main fuel valve opening time was an important factor. For stable operation, the main fuel valve opening time must be set one second before after driving the start turbine. Likewise, it was confirmed that the startup analysis can suggest an appropriate startup sequence for a stable startup.

• Journal of the Korean Society of Propulsion Engineers
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• v.19 no.5
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• pp.62-70
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• 2015

A liquid rocket engine system can cause rapid pressure and temperature variations during the startup period. Thus the startup analysis is required to reduce time and expense for successful development of liquid rocket engine through the startup prediction. In this study, a startup analysis simulator is developed for a staged combustion cycle engine powerpack. This simulator calculates propellant flow rates using pressure and flow rate balances. In addition, a rotational speed of turbopump is obtained as a function of time by mathematical modeling. A startup analysis result shows that the time to reach a steady-state and a rotational speed at the steady-state are 1.3 sec and 27,500 rpm, respectively. Moreover it can indicate proper startup sequences for stable operation.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.101-110
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• 1997

SVLIW processor architectures can resolve resource collisions and data dependencies between the instructions while scheduling VLIW instructions at run-time. As a result, long NOP word instructions can be removed from the object code produced for the processor. Thus, the occurrence of cache misses on the SVLIW processor would be lesser than that on the same cache size VLIW processor. Less frequent cache misses on the SVLIW processor would incur less frequent memory access, and thus, the total execution cycles to complete an application would be shortened compared with cases on the VLIW processor. Such a feature eventually compromises effects of longer instruction pipeline stages than those of the VLIW processor. In this paper, we formulate and compare two execution cycle models of the two architectures. A simulation results show that the longer memory access cycles when cache miss occurs, the total execution cycles of SVLIW processor would be shorter than those of VLIW processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.39-45
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• 2003

Design verification of VHDL models is getting difficult and has become a critical and time-consuming process in hardware design. Recent]y the methods using Bayesian estimation and stopping rule have been introduced to verify behavioral models and to reduce clock cycles. This paper presents two strategies to reduce clock cycles when using stopping rule in a VHDL model verification. The first method is that a semi-random variable is defined and the data that stay in the range of semi-random variable are skipped when stopping rule is running. The second one is to keep the old values of parameters when phases of stopping rule are changed. 12 VHDL models are examined to observe the effectiveness of strategies, and the simulation results show that more than about 25% of clock cycles is reduced by using the two proposed strategies with 0.6% losses of branch coverage rate.