• Journal of KIISE:Computing Practices and Letters
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• v.10 no.6
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• pp.460-471
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• 2004

Since the RTP is suitable for real-time data transmission in multimedia services like VoD, AoD, and VoIP, it has been adopted as a real-time transport protocol by RTSP, H.323, and SIP. Even though the RTP protocol stack for embedded systems has been in great need for efficient support of multimedia services, such a stack has not been developed yet. In this paper, we explain embeddedRTP which supports the RTP protocol stack at the kernel level so that it is suitable for embedded systems. Since embeddedRTP is designed to reside in the UBP module, existing applications which rely ell TCP/IP services can proceed the same as before, while applications which rely on the RTP protocol stack can request HTP services through embeddedRTp API. EmbeddedRTP stores transmitted RTP packets into per session packet buffer, using the packet's port number and multimedia session information. Communications between applications and embeddedRTP is performed through system calls and signal mechanisms. Additionally, embeddedRTP API makes it possible to develop applications more conveniently. Our performance test shows that packet-processing speed of embeddedRTP is about 7.5 times faster than that oi VCL RTP for multimedia streaming services on PDA in spite that its object code size is reduced about by 58% with respect to UCL RTP's.

• The KIPS Transactions:PartC
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• v.17C no.2
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• pp.197-204
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• 2010

An effective integration of web-based learning environment and mobile device technology is considered as a new challenge to the developers. The screen size, however, of the mobile device is too small, and its performance is too inferior. Due to the foregoing limit of mobile technology, displaying bulk data on the mobile screen, such as a cyber lecture accompanied with real-time image transmission on the web, raises a lot of problems. Users have difficulty in recognizing learning contents exactly by means of a mobile device, and continuous transmission of video stream with bulky information to the mobile device arouses a lot of load for the mobile system. Thus, an application which is developed to be applied in PC is improper to be used for the mobile device as it is, a player which is fitting for the mobile device should be developed. Accordingly, this paper suggests mobile presentation using transcoding techniques of the field concerned. To display continuous video frames of learning image, such as a cyber lecture or remote lecture, by means of a mobile device, the performance difference between high-resolution digital image and mobile device should be surmounted. As the transcoding techniques to settle the performance difference causes damage of image quality, high-quality image may be guaranteed by application of trial and error between transcoding and selected learning resources.

• Journal of the Korea Society of Computer and Information
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• v.17 no.8
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• pp.1-10
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• 2012

This paper proposes design space exploration methodology of many-core processors including multimedia specific instructions to support high-performance and low power ultrasound imaging for portable devices. To explore the impact of multimedia instructions, we compare programs using multimedia instructions and baseline programs with a same many-core processor in terms of execution time, energy efficiency, and area efficiency. Experimental results using a $256{\times}256$ ultrasound image indicate that programs using multimedia instructions achieve 3.16 times of execution time, 8.13 times of energy efficiency, and 3.16 times of area efficiency over the baseline programs, respectively. Likewise, programs using multimedia instructions outperform the baseline programs using a $240{\times}320$ image (2.16 times of execution time, 4.04 times of energy efficiency, 2.16 times of area efficiency) as well as using a $240{\times}400$ image (2.25 times of execution time, 4.34 times of energy efficiency, 2.25 times of area efficiency). In addition, we explore optimal PE architecture of many-core processors including multimedia instructions by varying the number of PEs and memory size.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2369-2379
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• 2013

A CMOS x-ray line scan sensor which is used in both medical imaging and non-destructive diagnosis is designed. It has a pixel array of 512 columns ${\times}$ 4 rows and a built-in DC-DC converter. The pixel circuit is newly proposed to have three binning modes such as no binning, $2{\times}2$ binning, and $4{\times}4$ binning in order to select one of pixel sizes of $100{\mu}m$, $200{\mu}m$, and $400{\mu}m$. It is designed to output a fully differential image signal which is insensitive to power supply and input common mode noises. The layout size of the designed line scan sensor with a $0.18{\mu}m$ x-ray CMOS image sensor process is $51,304{\mu}m{\times}5,945{\mu}m$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.1
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• pp.31-37
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• 2017

In this paper, we implemented for the development of a high output induction lamp system, which lamp design is optimized by gas type, mixing ratio, pressure and discharge tube size, amalgam type and mixing ratio, and characteristics of ferrite core in the lamp. It's the circuit design by improving the power factor and efficiency according to the driving method, which has analyzing the characteristics according to the waveform and frequency. Finally, luminaries design part for applying the optimal lighting system considering the surrounding environment, the characteristics of the lighting circuit for electrodeless lamp has analyzed and the improvement has been proceeded. In conclusion, the driving frequency has optimized at 135kHz with degrading $7{\sim}10^{\circ}C$ based on the results of the optical characteristics of the induction lamp on peak noise FET(Q3,Q4) damage.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.3
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• pp.533-543
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• 2018

In this paper, we propose an MILP-based method for Optimal Probability of Bit-based Differential Characteristic in SP(Substitution-permutation) ciphers based on Automatic Differential Characteristic Searching Method of Sasaki, et al. In [13], they used input/output variables and probability variables seperatably, but we simplify searching procedure by putting them(variables) together into linear inequalities. Also, In order to decrease the more linear inequalities, we choose Espresso algorithm among that used by Sasaki, et al(Quine-McCluskey algorithm & Espresso algorithm). Moreover, we apply our method to GIFT-64, GIFT-128, SKINNY-64, and we obtained results in the GIFT(Active S-boxs : 6, Probabilities : $2^{-11.415}$) compared with the existing one.(Active S-boxs : 5, Probabilities : unknown). In case of SKINNY-64, we can't find better result, but can find same result compared with the existing one.

• Journal of KIISE
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• v.41 no.10
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• pp.762-773
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• 2014

As the web of data is increasingly producing large RDFS datasets, it becomes essential in building scalable reasoning engines over large triples. There have been many researches used expensive distributed framework, such as Hadoop, to reason over large RDFS triples. However, in many cases we are required to handle millions of triples. In such cases, it is not necessary to deploy expensive distributed systems because logic program based reasoners in a single machine can produce similar reasoning performances with that of distributed reasoner using Hadoop. In this paper, we propose a scalable RDFS reasoner using logical programming methods in a single machine and compare our empirical results with that of distributed systems. We show that our logic programming based reasoner using a single machine performs as similar as expensive distributed reasoner does up to 200 million RDFS triples. In addition, we designed a meta data structure by decomposing the ontology triples into separate sectors. Instead of loading all the triples into a single model, we selected an appropriate subset of the triples for each ontology reasoning rule. Unification makes it easy to handle conjunctive queries for RDFS schema reasoning, therefore, we have designed and implemented RDFS axioms using logic programming unifications and efficient conjunctive query handling mechanisms. The throughputs of our approach reached to 166K Triples/sec over LUBM1500 with 200 million triples. It is comparable to that of WebPIE, distributed reasoner using Hadoop and Map Reduce, which performs 185K Triples/sec. We show that it is unnecessary to use the distributed system up to 200 million triples and the performance of logic programming based reasoner in a single machine becomes comparable with that of expensive distributed reasoner which employs Hadoop framework.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.252-259
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• 2007

With the rapid development of multimedia applications and wireless communication networks, consumer demand for video-over-wireless capability on mobile computing systems is growing rapidly. In this regard, this paper introduces YUV-aware instructions that enhance the performance and efficiency in the processing of color image and video. Traditional multimedia extensions (e.g., MMX, SSE, VIS, and AltiVec) depend solely on generic subword parallelism whereas the proposed YUV-aware instructions support parallel operations on two-packed 16-bit YUV (6-bit Y, 5-bits U, V) values in a 32-bit datapath architecture, providing greater concurrency and efficiency for color image and video processing. Moreover, the ability to reduce data format size reduces system cost. Experiment results on a representative dynamically scheduled embedded superscalar processor show that YUV-aware instructions achieve an average speedup of 3.9x over the baseline superscalar performance. This is in contrast to MMX (a representative Intel#s multimedia extension), which achieves a speedup of only 2.1x over the same baseline superscalar processor. In addition, YUV-aware instructions outperform MMX instructions in energy reduction (75.8% reduction with YUV-aware instructions, but only 54.8% reduction with MMX instructions over the baseline).

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.443-452
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• 2009

Although 32-bit architectures are becoming the norm for modern microprocessors, 16-bit ones are still employed by many low-end processors, for which small size and low power consumption are of high priority. However, 16-bit architectures have a critical disadvantage for embedded processors that they do not provide enough encoding space to add special instructions coined for certain applications. To overcome this, many existing architectures adopt non-orthogonal, irregular instruction sets to accommodate a variety of unusual addressing modes. In general, these non-orthogonal architectures are regarded compiler-unfriendly as they tend to requires extremely sophisticated compiler techniques for optimal code generation. To address this issue, we proposed a compiler-friendly processor with a new addressing mode, called the dynamic implied addressing mode(DIAM). In this paper, we will demonstrate that the DIAM provides more encoding space for our 16-bit processor so that we are able to support more instructions specially customized for our applications. And we will explain the advanced architecture which has improved performance. In our experiment, the proposed architecture shows 11.6% performance increase on average, as compared to the basic architecture.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.7
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• pp.305-317
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• 2008

As a mobile computing environment is rapidly changing, increasing user demand for multimedia-over-wireless capabilities on embedded processors places constraints on performance, power, and sire. In this regard, this paper proposes color media instructions (CMI) for single instruction, multiple data (SIMD) parallel processors to meet the computational requirements and cost goals. While existing multimedia extensions store and process 48-bit pixels in a 32-bit register, CMI, which considers that color components are perceptually less significant, supports parallel operations on two-packed compressed 16-bit YCbCr (6 bit Y and 5 bits Cb, Cr) data in a 32-bit datapath processor. This provides greater concurrency and efficiency for YCbCr data processing. Moreover, the ability to reduce data format size reduces system cost. The reduction in data bandwidth also simplifies system design. Experimental results on a representative SIMD parallel processor architecture show that CMI achieves an average speedup of 6.3x over the baseline SIMD parallel processor performance. This is in contrast to MMX (a representative Intel's multimedia extensions), which achieves an average speedup of only 3.7x over the same baseline SIMD architecture. CMI also outperforms MMX in both area efficiency (a 52% increase versus a 13% increase) and energy efficiency (a 50% increase versus an 11% increase). CMI improves the performance and efficiency with a mere 3% increase in the system area and a 5% increase in the system power, while MMX requires a 14% increase in the system area and a 16% increase in the system power.