• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.83-91
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• 2003

High-speed QPSK demodulator has been in important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes all-digital QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. All-digital QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tacking to fabricate FPGA chip. The testing results of the implemented onto CPLD-EPF10K100GC 503-4 chip show demodulation speed is reached up to 2.6[Mbps]. If it is implemented a CPLD chip with speed grade 1, the demodulation speed can be faster by about 5 times. Actually in case of designing by ASIC, its speed my be faster than CPLD by 5 times. Therefore, it is possible to fabricate the all-digital QPSK demodulator chipset with speed of 50[Mbps].

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.11a
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• pp.59-62
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• 2009

본 논문에서는 UHDTV(Ultra HDTV)를 위한 MPEG-2 TS(Transport Stream)의 다중화 기법 및 다중화 SW 툴의 설계 및 구현에 대해서 기술한다. 대용량의 UHD 비디오를 처리하기 위해서는 당분간 병렬처리에 기반한 코덱 구현이 불가피하며 이로 인해 다수의 비디오 비트스트림 간의 동기화 및 다중화가 요구된다. 본 논문에서는 4K(또는 8K) 해상도의 UHD 비디오가 4개의 화면으로 분할되어 각각 H.264/AVC로 부호화되고, 2 개의 5.1 채널의 오디오가 AC-3로 부호화되는 병렬처리 기반의 UHDTV의 TS 다중화를 고려한다. H.264/AVC를 전송하기 위한 MPEG-2 시스템(Systems) 확장 규격과 AC-3를 다중화하기 위한 ATSC 규격에 따라 PES 패킷화 및 TS 다중화 툴을 설계한다. 본 논문의 다중화 툴은 타이밍 모델을 만족하도록 T-STD(TS Systems Target Decoder)에 정의된 버퍼들의 상태를 모니터링 하면서 다중화 스케쥴링을 수행하고 한 TS 패킷의 전송 시간 단위로 H/W의 실시간 처리를 에뮬레이션(emulation) 한다. 또한 전체 다중화 구조에 있어서 재다중화(Re-multiplexing)의 포함 여부에 따른 장단점에 대해서 고찰한다. 상용 검증 툴 및 재생 툴을 통하여 구현한 TS 다중화 툴의 규격의 적합성 및 그 기능을 검증한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.792-797
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• 2013

This paper has derived the conversion loss according to the synchronized condition between the transmitted and locally generated spreading signals for the civil global positioning system (GPS) receiver in the heavy wideband Gaussian noise environments. From this, the outputs of the 2-bit nonuniform quantizer, which has the minimum conversion loss, is set to ${\pm}1$ and ${\pm}2$, while the quantization step size is approximated to the jamming-to-signal power ratio.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.504-512
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• 2010

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• Journal of IKEEE
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• v.17 no.3
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• pp.248-253
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• 2013

Frequency detector is a circuit that converts the frequency to a digital representation and finds its application in various fields such as modulator and synchronization circuitry. In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources. Also a delta-sigma frequency detector architecture is proposed. Through theoretical analysis and derived equations, the output noise is obtained, which is validated by simulation. The proposed all-digital frequency discriminator may be applied in the feedback path of the all-digital phase-locked loop.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.218-222
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• 2001

본 논문에서는 B-WLL 상향링크 수신기용 심볼 및 위상 동기 회로를 설계하였다. B-WLL 상향링크는 버스트 전송 방식이고, 변조 방식은 QPSK를 사용한다. 본 연구에서는 심볼율을 2.5 Msymbol/sec로 가정하였고, 디지털 Up/Down Converter를 이용한 IF 대역은 20 [MH]를 사용하였다. 수신필터는 25 탭, 7 비트 계수를 가지는 FIR 필터로 설계하였다. 심볼 타이밍 복구 회로는 Gardner 알고리즘을 이용하여 설계하였으며, 반송파 복구는 결정 지향 알고리즘을 이용하여 설계하였다. 설계된 알고리즘은 VHDL로 코딩되어 FPGA에 구현되었다. 실험에 사용된 FPGA는 ALTERA사의 APEX20KE 시리즈의 60만 게이트 FPGA이다. 구현된 복조기의 성능을 평가하기 위하여 모의실험 결과와 구현 결과를 비교하여 제시하였다. 그 결과로 주파수 오프셋과 위상 오프셋이 있는 경우에도 심볼 타이밍 복구 회로는 잘 동작을 하였으며, 주파수 오프셋이 심볼율의 0.12%까지 위상 동기회로가 잘 동작하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.12
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• pp.1248-1255
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• 2003

High-speed QPSK demodulator has been one important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes Zero-Crossing IF-level(ZCIF) QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. ZCIF QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tracking to fabricate FPGA chip. The testing results of the implemented onto CPLD-FLEX10K chip show demodulation speed is reached up to 2.6［Mbps］. Actually in case of designing by ASIC, its speed may be faster than CPLD by 5 times. Therefore, it is possible to fabricate the ZCIF QPSK demodulator with speed of 10 Mbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.1-7
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• 2000

Generally, one-dimensional fiber optic code-division multiple-access(CDMA) system is encoded and decoded using optical orthogonal codes(OOC’s), where two-dimensional fiber optic CDMA system uses optical orthogonal signature pattern codes(OOSPC’s) for parallel data link process. The OOSPC’s should have good autocorrelation and cross-correlation properties. However, if timing information or synchronization of OOSPC’s can be obtained by other means, the property of autocorrelation may not be restricted and we can increase the number of pattern codes. In this paper we introduce the fiber optic CDMA system for parallel transmission of two-dimensional data and investigate methods of generation of two-dimensional pattern codes. The probability density function of interference noise is calculated in interfering OOSPC’s of the users and the corresponding bit error rate is derived.. We compare each OOSPC’s by plotting bit error rate versus threshold values and the number of simultaneous users, from the result, we propose the optimal OOSPC’s conditions for the parallel transmission of two-dimensional data.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1868-1879
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• 1996

There are limitations to process high bandwidth traffic in B-ISDN with mesh- topology single bus architecture of current mobile communication system. And, it is impossible to import ATM switch using fixed length packet rather than variable length packet. Some implementations are able to process variable length packet, but there are some problems such as pre-processing for synchronization and bit delay. In this paper, we design a concentrator that can manipulate variable length packet without additional pre-process. There is on bit delay for packet starting signal in input interface, So it is more efficient to process packets, such that the concentrator can reduce he processing time as $\ulcornerlog2N\lrcorne＋1$ bit-time rather than N bit-time delay in ordinary concentrator. It is expected that the mobile communication system with partial mesh topology bus adopting the knockout switch architecture can process high bandwidth traffic in B-ISDN.