• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1735-1740
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• 2005

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1038-1041
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• 2005

In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.47-54
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• 2000

We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.617-620
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• 2002

본 논문에서는 single bank와 multi bank FIFO를 지원하는 CMOS FIFO memory compiler를 개발 검증하였다. 이 컴파일러를 사용해서 설계자는 구현하고자 하는 어플리케이션에 적합한 high speed, high density, low power를 갖는 on-chip memory를 빠른 시간에 만들어 낼 수 있으므로 설계 시간을 절약할 수 있다. 이와 더불어 설계된 FIFO 의 시뮬레이션을 지원하기위한 Verilog 시뮬레이션 모델을 제공하였다. 현재 FIFO를 구성하는 단위 셀들은 0.6um 3-metal 공정을 이용하여 설계하였으며 공정의 변화에 따라 대상 공정에 맞도록 단지 몇 개의 단위 셀만을 재 설계하고 그에 대한 정보를 갱신해줌으로써 공정의 변화에 대처 할 수 있도록 하였다. 설계된 컴파일러를 이용해 생성된 FIFO 는 표준 셀 라이브러리를 이용한 합성 가능한 FIFO에 대하여 $16bit{\times}16word$ FIFO에서 면적면에서 93%, 속도면에서 70%의 향상을 보였다.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.759-762
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• 1998

In this paper, a SL-DCVSL (static latched differential cascode voltage switch logic) circuit for the asynchronous pipeline is proposed. The proposed SL-DCVSL circuit is a slightly modified version of the DCVSL circuit, and used to improve the storage capability of the precharged functional blocks. The proposed SL-DCVSL has more robust storage characteristics compared to the conventional LDCVSL (latched DCVSL〔2〕). The operation of the proposed circuit is verified by simulating the asynchronous FIFO (First-In First-Out) structure.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.1
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• pp.14-26
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• 2011

In this paper, we've studied Optical Fiber Subscribe Transmit system. After receiving the ATM cell passing through the FIFO of the Asynchronous Transfer Method from the ATM Layer images to the VC4 signal payload passing through scrambling of the cell payload, HEC computation of the cell and inserting the Idle/Unassigned cell. At this time formed VC4 signal passing through the generating and inserting POH overhead at the same time indicating the start point of the cell by the H4 byte on the VC4 POH. This ATM cell transmits 155Mbps speed changing the optical signal after outputting the frame format at the STM-1 signal generation block through the AUG bus after generating J1 of the VC4 start point at the AU4 pointer generation block.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.05a
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• pp.12-15
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• 2018

비정형 데이터를 효율적으로 처리하기 위한 대표적인 오브젝트 스토리지로 OpenStack Swift가 있다. 하지만, 오브젝트 스토리지의 일관성 지원은 동기화 지연을 발생시키고 전체 성능에 영향을 미친다. 이런 문제는 기존 시스템에서 발생하는 페이지 스왑, 데이터 중복을 비휘발성 메모리를 사용함으로써 제거할 수 있고 오브젝트 서버의 성능 하락을 완화할 수 있다. 하지만, 비휘발성 메모리를 효율적으로 사용하기 위해서는 비휘발성 메모리 장치별 특성을 고려한 효율적인 데이터 배치가 필요하고 본 논문에서는 이를 위한 마이그레이션 기법을 제안한다. 마이그레이션 기법에서 사용하는 점수식은 First In First Out (FIFO)보다 정확도를 약 11% 향상시켰고, 기존 기법들보다 실행 시간은 42% 감소, 마이그레이션 횟수는 최대 24배 감소, 에너지 소비량은 9% 정도 절약하였다.