• 발명특허
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• v.15 no.10 s.176
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• pp.46-50
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• 1990

• 발명특허
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• v.29 no.8 s.338
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• pp.30-33
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• 2004

• Smart Media Journal
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• v.12 no.2
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• pp.83-90
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• 2023

The advent of quantum computers threatens the security of existing hash functions. In this paper, we confirmed the implementation results of quantum circuits for domestic/international hash functions, LSH, SHA2, SHA3 and SM3, and conducted a comparative analysis. To operate the existing hash function in a quantum computer, it must be implemented as a quantum circuit, and the quantum security strength can be confirmed by estimating the necessary quantum resources. We compared methods of quantum circuit implementation and results of quantum resource estimation in various aspects and discussed ways to meet quantum computer security in the future.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.133-138
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The signal through a small RC time constant circuit has almost same loop filter output voltage. The signal through a large RC time constant circuit has the average value of loop filter output voltage and does as a role of reference voltage to the comparator. The output of the comparator controls the sub-charge pump which provide a current to LPF. When the loop filter output voltage increases, the sub-charge pump discharges the loop filter and decreases loop filter output voltage. When the loop filter output voltage decreases, the sub-charge pump charges the loop filter and increases loop filter output voltage. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• Proceedings of the Korea Water Resources Association Conference
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• 2009.05a
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• pp.405-409
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• 2009

현재 하천의 유량측정을 위해 국내외에서 설치, 운영되고 있는 자동유량측정시설은 대부분 초음파유속계를 이용한 실시간 하천유량측정시스템이다. 이러한 초음파유속계는 도플러 방식 초음파유속계(ADVM)와 이동 시간차 방식 초음파유속계(UVM)로 구분되는데, 한강대교 등에 적용된 ADVM 방식에 비해 UVM 방식은 초음파 도달거리의 특성으로 인해 대부분 중소규모의 하천에 적용되어왔다. 이러한 UVM 방식을 하폭이 넓고 홍수시 수위변화가 심한 대규모하천에 적용하기 위해서는 여러 회선을 다층으로 구성하여 설치할 필요가 있는데, 한강의 여주지점은 16개의 회선을 5개의 층으로 구성하여 측정의 정확도를 높이고 홍수시 수위상승시에도 다양한 회선으로 유속을 측정할 수 있도록 하였다. 본 연구에서는 여주지점에 설치되어 운영 중에 있는 이동 시간차 방식 자동유량측정시설의 운영결과를 검토하고 측정치에 대한 검증을 위해 2008년 1월부터 12월까지의 유량측정결과를 검토하였다. 평 저수시는 유속계와 ADCP 이동보트를 이용한 연속측정결과와 비교하였으며 홍수시에는 봉부자 측정결과와 비교하였다. 기존 실측은 2008년 2월부터 12월까지 저수위 및 중 고수위에 걸쳐 실시하였으며, 프라이스유속계 22회, 이동식 ADCP 6회 그리고 부자를 이용한 방법 6회등, 총 34회가 이루어졌으며, 비교 결과 수위 1.5m 이하의 저 평수기에 평균 5.5%의 오차를 보였으며, 홍수시 검증측정유량과의 비교결과 7.6%의 오차를 보였다.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1218-1219
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• 2011

본 논문은 KA555 Timer을 이용한 PWM회로로 구성된 아날로그 방식의 DC-DC Buck Converter와 AVR ATmega128를 이용한 PWM회로로 구성된 디지털 방식의 Buck Converter을 설계하여 각각의 특성을 비교 분석하였다. 제안된 컨버터들은 공통적으로 전원을 공급받아 전압분압회로를 통해 DC-DC Buck Converter의 PWM 제어회로부에 공급되며, 아날로그방식 컨버터의 제어부는 KA555 timer을 이용하여 구형파회로와 미분회로를 구성하고, 출력된 삼각파와 정현파를 KA555 timer을 이용하여 PWM파형으로 제어한다. 디지털방식의 컨버터는 AVR RISC 8-bit 마이크로프로세서 ATmega128을 이용하여 PWM 제어부를 구성하고 이를 LCD창을 통해 그 값을 확인할 수 있도록 설계하였다. 본 논문에서는 두 가지 방식의 제어부를 구성하여 제작 및 실험함으로써, 각각의 장단점을 비교하여 시스템 구성시 요구조건인 소형경량, 단가저감, 효율 등을 비교하여 그 상황에 맞는 설계가 가능할 것이다.

• Journal of the Korean Vacuum Society
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• v.10 no.1
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• pp.72-80
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• 2001

In this paper, we present a systematic method of extracting the input parameters of poly-Si TFT(Thin-Film Transistor) for Spice simulations. This method has been applied to two different types of poly-Si TFTs such as ELA (Excimer Laser Annealing) and SMC (Silicide Mediated Crystallization) with good fitting results to experimental data. Among the Spice circuit simulators, the PSpice has the GUI(graphic user interface) feature making the composition of complicated circuits easier. We added successfully the poly-Si TFT model of AIM-Spice to the PSpice simulator, and analyzed easily to compare the electrical characteristics of pixels without or with the line RC delay. In the comparative results, the ELA poly-Si TFT is superior to the SMC poly-Si TFT in the charging time and the kickback voltage for the TFT-LCD (Thin Film Transistor-Liquid Crystal Display).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.740-749
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• 2015

In the visible light (VL) communication based on the conventional LED lights, depending on the increase of the communication range, the signal received at the photodiode of the VL receiver has usually the random distorted and decreased amplitude due to the path loss and fading effects of the VL channel. In order to overcome this problem, we propose, design, and implement the visible light communication circuit based on the comparator threshold voltage, where has a built-in distance compensation function. In addition, the performance of the proposed technique is evaluated and analyzed depending on the distance and communication speed through comparing the proposed VLC system based on the threshold voltage with the conventional one.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.43-49
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• 1995

In this paper a space search technique is used to detect and locate the faults of the circuit interconnections. The circuit interconnections are represented by the tree structure and the tree space is searched to detect and locate the open faults of the circuit interconnections. The breadth search is used to detect the open faults and reduce the space size. The depth search is used to locate the open faults.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.493-502
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• 2001

This paper propose a new built-in current sensor(BICS) for current testing that has some advantages compared with conventional logic testing. The designed BICS detects the fault in circuit under test (CUT) and makes a Pass/Fail signal by comparison between CUT current and duplicated inverter current. The proposed circuit consists of a differential amplifier, a comparator and a inverter. It requires 10 MOSFETs and 3 inverters. Since the designed BICS do not require the extra clock, the added extra pin is only one output pin. The mode selection is not used in this circuit. Therefore we can apply the circuit to on-line testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When CUT is a 8$\times$8 parallel multiplier, area overhead of the BICS is about 4.34%.