• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.5
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• pp.1-10
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• 1998

Satellite communication is getting more important in the coming 21st century because of its wide areas sevice capability, ease of access, and fast channel establishment. As such, satellite communication networks will be the basis of the global communication system in cooperation with the ground ATM networks. In this paper, we consider an efficient transmission methodology of ATM cells over the satellite communication channel. We first analyze possible bottlenecks and performance deterioration factors in the case, and then propose an enhanced cell trasmission mechanism. In order to use satellite channel for ATM cell transmission, the application of complicated channel coding is inevitable. However, the forwared error control such as convolutional encoding brings forth burst errors, which calls for the application of some kind of interleaving mechanism to randomize the burst errors at the receiver. Another aspect which should b econsidered in satellite communication system is the inherent transmission delay, which can be very considered in satellite communication system is te inherent transmission delay, which can be very critical to the delay-sensitive ATM traffic. Therefore, we propose that the processing delay at the block interleaving stage should be controlled propose a variable-size block interleaving mechanism which utilizes the predicted transmission delay for each traffic in the queues of the transmitter. According to the computer simulation, the proposed mechanism could improve the overall performance by drastically reducing the ATM cell drop rate owing to the excessive transmission delay.

• The KIPS Transactions:PartA
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• v.18A no.4
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• pp.135-142
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• 2011

This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.36-46
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• 2017

The turbo code, an error correction code, needs a long decoding time since the same decoding process must be repeated several times in order to obtain a good BER performance. Thus, parallel processing may be used to reduce the decoding time, in which case there may be a memory contention that requires additional buffers. The QPP interleaving has been proposed to avoid such case, but there is still a possibility of memory contention when a decoder is constructed using the so-called double flow technique. In this paper, we propose an even-odd cross mapping technique to avoid memory conflicts even in decoding using the double-flow technique. This method uses the address generation characteristic of the QPP interleaving and can be used to implement the interleaving circuit between the decoding blocks and the LLR memory blocks. When the decoder implemented by applying the double flow and the proposed methods is compared with the decoder by the conventional MDF techniques, the decoding time is reduced by up to 32% with the total area increase by 8%.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.43-49
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• 2014

In this paper, we consider the performance evaluation of space time block code (STBC)) with coordinate interleaved orthogonal design (CIOD) over time selective channel. In case of quasi static channel, STBC-CIOD satisfies full rate and full diversity (FRFD) property with the single symbol decoding. However in the time selective channel, the symbol interference degrades the system performance when we employ the single symbol decoding. We derive the union bound of the symbol error probability by evaluating the pairwise error probability in the first order Markov channel. We also present simulation results of STBC-CIOD with QPSK.

• Journal of Korea Multimedia Society
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• v.6 no.5
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• pp.769-777
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• 2003

We present a striping technique that MPEG-1 video streams ell a disk array can be efficiently played back at different resolution levels. For the MPEG-1 compression algorithm, the proposed multi-level encoding technique first partitions the parent video stream in the temporal dimension. Each frame in the sub-stream is then Partitioned in the chroma dimension yielding a low resolution and a residual component. The multimedia server stores blocks of different components on consecutive disks in a round robin manner. As a result, the lower the resolution level being maintained, the smaller is the number of disks accessed by each client. To effectively utilize a disk array and to maximize the number of clients that can be serviced simultaneously, the proposed technique interleaves the storage of the component of sub-streams among the disks in the array We empirically validate and evaluate this striping technique through simulation in order to show the improvement of its performance on the server.

• The KIPS Transactions:PartC
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• v.10C no.1
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• pp.77-86
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• 2003

This paper describes the new method for Internet multicast routing protocols using MPLS (Multiprotocol Label Switching) networks. Internet multicast routing protocols are divided into three categories in terms if tree types and tree characteristics : a shortest path tree a shared tree and hybrid tree types. MPLS should support various multicast mechanisms because of extremely different IP multicast architectures, such as uni-/bi-directional link, Flooding/prune tree maintenance mechanism. the existence of different tree types with the same group, etc. There are so many problems over MPLS multicast that the solutions can't be easily figured out. In this Paper, we make a few assumptions on which the solutions of IP multicast routing protocols over MPLS networks are given. A broadcasting label is defined for the shortest path tree types. Cell interleaving problems of the shared tree types is solved by using block-based transmission mechanism. Finally, the existing hybrid-type multicast routing protocol is reasonably modified Shortest Path tree type to support MPLS multicast. It has been shown that these modifications give better performance (transmission delay) than the orignal method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1571-1578
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• 1999

In this paper, we present the Modulator Channel Card and VLSI chip for the Radio Transceiver Unit (RTU) of direct sequence code division multiple access (DS-CDMA) Wireless Local Loop (WLL) System. The Modulator Channel Card is designed and implemented using ASIC's, FPGA's and DSP's. The ASIC, compliance with Common Air Interface specification proposed by ETRI, has 40K gates which is designed to operate at 32MHz, and is fabricated using $0.6\mu\textrm{m}$ CMOS process. The ASIC carries out for I- or Q- phase data channel signal processing at a time, where each data channel processing consists of channel coding, block interleaving, scrambling, Walsh modulation, Pseudo-Noise (PN) spreading, and baseband filtering. The Modulator Channel Card has been integrated as a part of RTU of WLL system and is confirmed that it meets all functional and performance requirements.